ahdlLib opamp model vref pin

Hi Olivier,

They're old, but that doesn't necessarily mean that there needs to be a more modern way necessarily. The models in bmslib are newer; the modelwriter models are similar in concept (although structured slightly differently).

It's just that because they are old, the developers are long gone and it's unlikely any new documentation is likely to be written. I did check resources such as the Designer's Guide web site but there didn't seem to be anything other than an ideal opamp model in the models listed there.

So I would suggest you look at both bmslib and modelwriter (as that can allow you to tailor the models to what you need).

Regards,

Andrew.

From the code it seems that vref is reference node for output voltage. However, when I run the test Vout doesn't change when vref change over all range. So what is the function of it?

This is the nest list:

// Generated for: spectre
// Generated on: Jun 16 16:55:17 2018
// Design library name: TEST
// Design cell name: Test_opamp
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: TEST
// Cell name: Test_opamp
// View name: schematic
I0 (Vout VREF Vin net03 AVDD AVSS) opamp gain=1M freq_unitygain=30M rin=1T \
vin_offset=0 ibias=0 iin_max=100u rout=10 vsoft=0.5 slew_rate=1M
V5 (net07 0) vsource dc=1 type=dc
VREF1 (VREF 0) vsource dc=0 type=dc
AVSS1 (AVSS 0) vsource dc=0 type=dc
AVDD1 (AVDD 0) vsource dc=5 type=dc
Vin1 (Vin net07) vsource mag=1 phase=0 type=sine ampl=100.0m sinephase=0 \
freq=1K
R1 (net03 Vout) resistor r=9K
R0 (net07 net03) resistor r=1K
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=10m write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/home3/tool/IC616/tools/dfII/samples/artist/ahdlLib/opamp/veriloga/veriloga.va"

It's effectively an internal common-mode node; it doesn't have much (if any - I didn't exhaustively check it through) influence on the output (it might if the ibias is large enough, or you're slew rate limiting - I didn't really check through the equations in the Verilog-A code. You have the code, so you could work through that yourself.

Andrew

Thank you. Actually I checked the code line by line and if I understood it correctly it is a common mode voltage for the output. However, it is strange that output common mode voltage doesn't change when I vary the vref. 

BaaB said:

However, it is strange that output common mode voltage doesn't change when I vary the vref.

It's not strange at all. The opamp DC output voltage is defined by your feedback circuitry. Given that the two input pins must be (almost) equal (because of the high gain), and the dc level of the sinusoidal source is 0V, the voltage across both R0 and R1 will be 0V too. If there had been a dc component in the sine source, the voltage across R0 would end being the same as that DC component, and so the DC level of the output voltage would be 10 times higher (plus the 1V from V5). For example, if you set dc on Vin1 to 0.05 then the DC level at the output of the amplifier would be 0.5*10+1=1.5V.

That's how opamps work. The Vref is just used in the output stage; it does not set the DC level of the output of the amplifier otherwise it would not operate correctly as an opamp.

Regards,

Andrew.

BaaB said:

However, it is strange that output common mode voltage doesn't change when I vary the vref.

It's not strange at all. The opamp DC output voltage is defined by your feedback circuitry. Given that the two input pins must be (almost) equal (because of the high gain), and the dc level of the sinusoidal source is 0V, the voltage across both R0 and R1 will be 0V too. If there had been a dc component in the sine source, the voltage across R0 would end being the same as that DC component, and so the DC level of the output voltage would be 10 times higher (plus the 1V from V5). For example, if you set dc on Vin1 to 0.05 then the DC level at the output of the amplifier would be 0.5*10+1=1.5V.

That's how opamps work. The Vref is just used in the output stage; it does not set the DC level of the output of the amplifier otherwise it would not operate correctly as an opamp.

Regards,

Andrew.