• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Cell only in schematic but not layout

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 13424
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cell only in schematic but not layout

itos
itos over 8 years ago

Hi,

Is is possible to have a cell that only exists in the schematic but not in the layout and still have it LVS clean?

I give one example where I know that it works: noConn from basic.

I give a couple of examples where I would fine this useful:

1.) I created a "wire_model" cell that just implements first order parasitic estimations for long wires in my model. For Layout (incl parasitic extraction) this should just be replaced by a short.

2.) I have some dummy connectors which just route one pin to another. To avoid warnings and errors I just place a 0 Ohm resistor or a vdc with 0V in between. Clearly this should be ignored in layout because there is an actual wire

3.) My standard cell inverters have "output" as pin type but I need them to connect in parallel to achieve my desired strength. For example, I would have INV1<1:2>, INV2<1:10> etc.  In order to evoid warnings, I can also place them individually in the schematic and put a res with 0 Ohm between the outputs.

Thanks!

  • Cancel
Parents
  • Quek
    Quek over 8 years ago

    Hi itos

    Yes, it is possible. E.g. you can use the following cmds if you are using PVS:

    lvs_black_box wireModelCell -source
    lvs_filter_device wireModelCell -source -short PLUS MINUS


    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Quek
    Quek over 8 years ago

    Hi itos

    Yes, it is possible. E.g. you can use the following cmds if you are using PVS:

    lvs_black_box wireModelCell -source
    lvs_filter_device wireModelCell -source -short PLUS MINUS


    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information