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Marking nets in cadence showing shorts

anandmohan

HI ,

When I am trying to mark nets in cadence to verify routing i am am seeing shorts. Cadence version is IC6.1.7-64b-500.7 . Marking the nets is also highlighting other unconnected nets, but LVS is going clean so there is no physical connection b/w them. Is there any way to solve this issue or any work around.

Regards

Anand Mohan

Parents

  • Hi Anand,

    it realy depends how the shorts are created to solve that. What we usually see, is that MOS transistors are shorting nets via the common Drain-Source active area shape.

    If this is the case for you, there are two ways around that. 

    You could disable the M1/Active  Via in the MarkNet Setup (F3)  or you can define a stop condition when the active is overlapped by poly (Gate), that is also done in the
    MarkNet submenu (F3).


    Regards,

    Marc

Reply

  • Hi Anand,

    it realy depends how the shorts are created to solve that. What we usually see, is that MOS transistors are shorting nets via the common Drain-Source active area shape.

    If this is the case for you, there are two ways around that. 

    You could disable the M1/Active  Via in the MarkNet Setup (F3)  or you can define a stop condition when the active is overlapped by poly (Gate), that is also done in the
    MarkNet submenu (F3).


    Regards,

    Marc

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