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Marking nets in cadence showing shorts

anandmohan

HI ,

When I am trying to mark nets in cadence to verify routing i am am seeing shorts. Cadence version is IC6.1.7-64b-500.7 . Marking the nets is also highlighting other unconnected nets, but LVS is going clean so there is no physical connection b/w them. Is there any way to solve this issue or any work around.

Regards

Anand Mohan

  • Hi Anand,

    it realy depends how the shorts are created to solve that. What we usually see, is that MOS transistors are shorting nets via the common Drain-Source active area shape.

    If this is the case for you, there are two ways around that. 

    You could disable the M1/Active  Via in the MarkNet Setup (F3)  or you can define a stop condition when the active is overlapped by poly (Gate), that is also done in the
    MarkNet submenu (F3).


    Regards,

    Marc

  • HI Marc,

    I have already disabled M1/Active and poly connection. But highlighting is showing short.

    Regards
    Anand

  • Hi Anand,


    to get rid of the short we have to identify the source of it. Maybe it  shorts over metal/poly resistors?

    If yes, see if they have any kind of recognition layer you could use as stopping shape.

    Marc

  • Is this in Layout XL? Do the annotation browser and navigator show shorts as well? This can happen sometimes when instances pick up some bad connectivity and it sticks. In those cases I end up selecting the suspected instance and connectivity->propagate nets and make sure things are right.

  • The smart thing about MarkNet is, that it is ignoring the connectivity information/terminals/netnames on wires and instances. It just
    recognizes the layer stack and works up and down the list with the given vias.

  • HI Marc,
    I have poly resistors in my layout. But since LVS is going clean there can't be any shorts. Also i have disabled M1-PO and M1-OD connections in mark net option.

    I didn't get your second point, can you please elaborate

    Sorry for the delay in replying

    Regards
    Anand
  • HI Dan

    I am using Layout XL only. annotation browser and navigator is not showing any shorts and also LVS went clean .In my layout VDD and VSS are showing as shorts, so i am not sure where to begin with since many devices are connected to VDD and VSS.

    Regards
    Anand
  • Hi Anand,

    MarkNet is not an extraction tool. It wont detect/extract devices. So being LVS clean does not have any meaning for MarkNet. Like I said, MarkNet nly knows the layeer stack: Poly Cut M1 Via1 M2 Via2 M3 ....... If you click on a M1 shape it will mark all M1 shapes touched by that one, will look for all the touched Via1 shapes, mark them, will look for all M2 shapes touched by these Via1 shapes ..... you get the idea. It wont stop at hierarchies or devices unless you define stop conditions or disable the vias.

    Kind regards,
    Marc
  • HI Marc,
    I got the concept, thank you for that. But the problem I am facing is marknet is highlighting nets which does not have any physical connection between them, for eg power and ground nets which is not connected at all (that's why I specified LVS is going clean). I have disabled M1-poly and M1-OD, so there is no way it connection can happen through diffusion or poly.

    Regards
    Anand
  • Hi Anand,

    unless it is a bug in the software, MarkNet obviously sees a connection somewhere. Don't know how to help you further without repeating myself.
    Switch off all vias but one run MarkNet, enable the next...repeat.. , maybe this is worth a try.

    Marc

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