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Layout Netlist and Topcell Netlist shows correct connections but LVS does not pass!!!

mehdina94rm

Hi,


I  am generating the topcel netlist from schematic and layout netlist from layout. I have checked both of them. Topcell netlist has an "X" before each component name which I should eliminate them manually to check the LVS. Netlists show correct connections in the layout but the LVS gives me error and even it says that I have no pins and even the number of nodes are not matched. I have designed a simple voltgae divider and did the layout to make sure whether the problem is with my Cadence or not. But it did not work, too. I have attached my Schematic, Layout and netlists. Please help me since the deadline is so close to me.

Regards,

Mehdi


  Error:    Different numbers of ports (see below).
  Error:    Different numbers of nets (see below).
  Error:    Different numbers of instances (see below).
  Error:    Connectivity errors.

LAYOUT CELL NAME:         test
SOURCE CELL NAME:         test

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              0         3    *

 Nets:               3         3

 Instances:          0         2    *    R (2 pins)
                     2         0    *    rppolyl (2 pins)
                ------    ------
 Total Inst:         2         2


NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              0         3    *

 Nets:               2         3    *

 Instances:          0         2    *    R (2 pins)
                     1         0    *    rppolyl (2 pins)
                ------    ------
 Total Inst:         1         2


       * = Number of objects in layout different from number in source.



**************************************************************************************************************
                               INFORMATION AND WARNINGS
**************************************************************************************************************


                  Matched    Matched    Unmatched    Unmatched    Component
                   Layout     Source       Layout       Source    Type
                  -------    -------    ---------    ---------    ---------
   Ports:               0          0            0            3

   Nets:                0          0            2            3

   Instances:           0          0            0            2    R(RPPOLYL)
                        0          0            1            0    rppolyl
                  -------    -------    ---------    ---------
   Total Inst:          0          0            1            2


o Statistics:

   2 series layout resistors were reduced to 1.  1 connecting net was deleted.



  • Hi Mehdi,

    your layout seem not to recognize your ports (in/out/vss). There is probably something wrong with them.

    Right layer? ( metal1 drw)  Right object type? ( create them with  Create -> Pin )

    Having the number of ports right between schematic and layout is the very first thing you need to ensure,

    because the LVS tool uses them to analyze your network.

    From the picture it seems there are some markers on the shapes. What is the info on these markers ? ( Annotation Browser Assistant )

    Are you sure you picked up the right layer for the layout connections?  These shapes look not like metal shapes at all,

    metal is usually displayed with filled  pattern.

    Marc

  • Hi Marc,

    Thanks a lot for your quick response. Regarding thee Pins, I have brought the pins from "Generate All from Source" in Layout GXL window. They are correct. But I do not know why Cadence do not consider them in the Netlist.

    I have fixed the issue with the markers. I have used M1 (metal one) and I am sure that it is correct. (Besides, if you see the netlist, it is obvious that the connections are correct). Do you have any other suggestions?

    Regards,

    Mehdi

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