Layout Netlist and Topcell Netlist shows correct connections but LVS does not pass!!!

Hi,

I  am generating the topcel netlist from schematic and layout netlist from layout. I have checked both of them. Topcell netlist has an "X" before each component name which I should eliminate them manually to check the LVS. Netlists show correct connections in the layout but the LVS gives me error and even it says that I have no pins and even the number of nodes are not matched. I have designed a simple voltgae divider and did the layout to make sure whether the problem is with my Cadence or not. But it did not work, too. I have attached my Schematic, Layout and netlists. Please help me since the deadline is so close to me.

Regards,

Mehdi

  Error:    Different numbers of ports (see below).
  Error:    Different numbers of nets (see below).
  Error:    Different numbers of instances (see below).
  Error:    Connectivity errors.

LAYOUT CELL NAME:         test
SOURCE CELL NAME:         test

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              0         3    *

 Nets:               3         3

 Instances:          0         2    *    R (2 pins)
                     2         0    *    rppolyl (2 pins)
                ------    ------
 Total Inst:         2         2


NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              0         3    *

 Nets:               2         3    *

 Instances:          0         2    *    R (2 pins)
                     1         0    *    rppolyl (2 pins)
                ------    ------
 Total Inst:         1         2


       * = Number of objects in layout different from number in source.



**************************************************************************************************************
                               INFORMATION AND WARNINGS
**************************************************************************************************************


                  Matched    Matched    Unmatched    Unmatched    Component
                   Layout     Source       Layout       Source    Type
                  -------    -------    ---------    ---------    ---------
   Ports:               0          0            0            3

   Nets:                0          0            2            3

   Instances:           0          0            0            2    R(RPPOLYL)
                        0          0            1            0    rppolyl
                  -------    -------    ---------    ---------
   Total Inst:          0          0            1            2


o Statistics:

   2 series layout resistors were reduced to 1.  1 connecting net was deleted.