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Parasitic extraction for interconnects

Fabio23

Hello all,

I need to run Calibre parasitic extraction (PEX) for some interconnects which are basically a combination of metal layers and vias. So no schematic corresponds to that, and I just have a layout consisting of metal layers. That is why LVS can not be run for that, and no PEX result can be obtained. I realized that we may be able to use some dummy resistors in the schematic (in the PDK that I use, I think they are called "lvsres") to create a dummy schematic. But "lvsres" has no layout in the technology library, it's just a symbol, so again no LVS can be run I assume. Does anyone know how to work with "lvsres", or how to run PEX for a cell with no schematic?

Thank you

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  • Fabio23
    Thank you Frank. PDK manual doesn't provide any information regarding that, I was hoping to find out how it's done in other technologies (the special layer) and employ that in ours.
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  • Fabio23
    Thank you Frank. PDK manual doesn't provide any information regarding that, I was hoping to find out how it's done in other technologies (the special layer) and employ that in ours.
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