Stats

  • Locked Locked
  • Replies 3
  • Subscribers 127
  • Views 17915
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Parasitic extraction for interconnects

Fabio23

Hello all,

I need to run Calibre parasitic extraction (PEX) for some interconnects which are basically a combination of metal layers and vias. So no schematic corresponds to that, and I just have a layout consisting of metal layers. That is why LVS can not be run for that, and no PEX result can be obtained. I realized that we may be able to use some dummy resistors in the schematic (in the PDK that I use, I think they are called "lvsres") to create a dummy schematic. But "lvsres" has no layout in the technology library, it's just a symbol, so again no LVS can be run I assume. Does anyone know how to work with "lvsres", or how to run PEX for a cell with no schematic?

Thank you

Parents
  • Fabio23
    Thank you Frank. PDK manual doesn't provide any information regarding that, I was hoping to find out how it's done in other technologies (the special layer) and employ that in ours.
Reply
  • Fabio23
    Thank you Frank. PDK manual doesn't provide any information regarding that, I was hoping to find out how it's done in other technologies (the special layer) and employ that in ours.
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.