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Parasitic extraction for interconnects

Fabio23

Hello all,

I need to run Calibre parasitic extraction (PEX) for some interconnects which are basically a combination of metal layers and vias. So no schematic corresponds to that, and I just have a layout consisting of metal layers. That is why LVS can not be run for that, and no PEX result can be obtained. I realized that we may be able to use some dummy resistors in the schematic (in the PDK that I use, I think they are called "lvsres") to create a dummy schematic. But "lvsres" has no layout in the technology library, it's just a symbol, so again no LVS can be run I assume. Does anyone know how to work with "lvsres", or how to run PEX for a cell with no schematic?

Thank you

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  • drdanmc
    look in the PDK for metal resistors. It would not be unusual to have them be filed under "resistor" category in a PDK and/or have names like rm1/rm2/etc or rmet1/rmet2/etc. And if this doesn't exist, you likely would have to add one. It is not too hard. A typical way would be a layer called something like "rrec" (for "resistor recognition") or "rmdummy"or "resmark". Then create a purpose for each metal layer. Then your device recognition just needs to look for metal+recognition layer. Then you can put one of these in series with a metal line and extract resistance between two pins on the same piece of metal.
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  • drdanmc
    look in the PDK for metal resistors. It would not be unusual to have them be filed under "resistor" category in a PDK and/or have names like rm1/rm2/etc or rmet1/rmet2/etc. And if this doesn't exist, you likely would have to add one. It is not too hard. A typical way would be a layer called something like "rrec" (for "resistor recognition") or "rmdummy"or "resmark". Then create a purpose for each metal layer. Then your device recognition just needs to look for metal+recognition layer. Then you can put one of these in series with a metal line and extract resistance between two pins on the same piece of metal.
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