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How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?

iguerra

Hi,

I would like to know if is possible to avoid compiling the Verilog/sytemVerilog views every time you generate an AMS netlist in ADE-L (based on a config file with a sytemVerilog template).

The compilation time is extremely long and I only want  to confirm if there is no netlist errors (no simulating).

Thanks.

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  • Andrew Beckett

    On the Simulation->Netlist and Run Options for AMS there are options for Compile and Elaborate being incremental. This is true whether you are using UNL, OSS or CBN netlisting modes. Also do you have the "clean" option enabled?

    Put simply, what options do you have on that form? (which netlist and run mode are you using, what are the compile and elaborate and clean settings set to?)

    Oh, and which IC subversion are you using?

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    On the Simulation->Netlist and Run Options for AMS there are options for Compile and Elaborate being incremental. This is true whether you are using UNL, OSS or CBN netlisting modes. Also do you have the "clean" option enabled?

    Put simply, what options do you have on that form? (which netlist and run mode are you using, what are the compile and elaborate and clean settings set to?)

    Oh, and which IC subversion are you using?

    Regards,

    Andrew.

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