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How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?

iguerra
iguerra over 8 years ago

Hi,

I would like to know if is possible to avoid compiling the Verilog/sytemVerilog views every time you generate an AMS netlist in ADE-L (based on a config file with a sytemVerilog template).

The compilation time is extremely long and I only want  to confirm if there is no netlist errors (no simulating).

Thanks.

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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    On the Simulation->Netlist and Run Options for AMS there are options for Compile and Elaborate being incremental. This is true whether you are using UNL, OSS or CBN netlisting modes. Also do you have the "clean" option enabled?

    Put simply, what options do you have on that form? (which netlist and run mode are you using, what are the compile and elaborate and clean settings set to?)

    Oh, and which IC subversion are you using?

    Regards,

    Andrew.

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  • iguerra
    iguerra over 8 years ago

    Hi Andrew,

    The version I am using is ICADV12.3. In the sections of the "Netlist and Run Options" I have:

    - NETLIST AND RUN MODE: selected "Cellview-based netlister with ncvlog, ncelab, nsim".

    - RUN OPTIONS: intentionally with the hope to avoid compiling, I have deselected ALL the check boxes in this section ("Compile incremental", "Elaborate incremental", "Simulate", "Clean snapshot and pack files" and "Compile VerilogA as Verilog-AMS" are unchecked).

    - SIMULATION MODE: default selected "Batch (normal)".

    -SAVE AND RESTART OPTIONS: Nothing set nor selected.

    By the way, in the past, one method that worked to me for avoiding compile Verilog/SV views when I netlisted in ADE-L, was to unload the incisive module before opening Virtuoso, then a lot of warnings/errors appeared in the CIW when I netlisted but the netlist process was very fast and the it was correctly generated if there was not netlist errors.

    Other thing I have tried, but not worked, was to set to the "vmsNcvlogExecutable" a fake path/name for ncvlog but the netlist is still compiling and it seems that was only affecting to the compiling process when you close a Verilog/SV view after editing (and then the view could not be closed. that was a really mess, a lot of windows open and they could not be closed because the compiling error).


    Thanks.

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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    First of all, cell-based is obsolete nowadays - you really should move to using UNL (especially with recent versions, as you're presumably using if using ICADV - you didn't say which number though). However, regardless of that...

    1. Unchecking the "incremental" options will just cause it to compile all, I think. So you should check the incremental options.
    2. There normally isn't a "clean snapshot and pak files" option with cell-based netlisting.
    3. The method you said about unloading the incisive module makes absolutely no sense to me. Some level of compilation is required to allow it to see hierarchy underneath textual views.
    4. The vmsNcvlogExecutable is related to when you are "checking and saving" the textual view - nothing to do with netlisting. So messing with that makes no sense either.

    One thing to be aware of is that it may still call ncvlog during netlisting - sometimes this may take little time as it's incremental though.

    However, you really should explore moving to using the Unified Netlister (UNL) technology instead.

    Regards,

    Andrew.

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