• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. How to avoid compiling Verilog/sytemVerilog views every...

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 3279
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?

iguerra
iguerra over 8 years ago

Hi,

I would like to know if is possible to avoid compiling the Verilog/sytemVerilog views every time you generate an AMS netlist in ADE-L (based on a config file with a sytemVerilog template).

The compilation time is extremely long and I only want  to confirm if there is no netlist errors (no simulating).

Thanks.

  • Cancel
Parents
  • iguerra
    iguerra over 8 years ago

    Hi Andrew,

    The version I am using is ICADV12.3. In the sections of the "Netlist and Run Options" I have:

    - NETLIST AND RUN MODE: selected "Cellview-based netlister with ncvlog, ncelab, nsim".

    - RUN OPTIONS: intentionally with the hope to avoid compiling, I have deselected ALL the check boxes in this section ("Compile incremental", "Elaborate incremental", "Simulate", "Clean snapshot and pack files" and "Compile VerilogA as Verilog-AMS" are unchecked).

    - SIMULATION MODE: default selected "Batch (normal)".

    -SAVE AND RESTART OPTIONS: Nothing set nor selected.

    By the way, in the past, one method that worked to me for avoiding compile Verilog/SV views when I netlisted in ADE-L, was to unload the incisive module before opening Virtuoso, then a lot of warnings/errors appeared in the CIW when I netlisted but the netlist process was very fast and the it was correctly generated if there was not netlist errors.

    Other thing I have tried, but not worked, was to set to the "vmsNcvlogExecutable" a fake path/name for ncvlog but the netlist is still compiling and it seems that was only affecting to the compiling process when you close a Verilog/SV view after editing (and then the view could not be closed. that was a really mess, a lot of windows open and they could not be closed because the compiling error).


    Thanks.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • iguerra
    iguerra over 8 years ago

    Hi Andrew,

    The version I am using is ICADV12.3. In the sections of the "Netlist and Run Options" I have:

    - NETLIST AND RUN MODE: selected "Cellview-based netlister with ncvlog, ncelab, nsim".

    - RUN OPTIONS: intentionally with the hope to avoid compiling, I have deselected ALL the check boxes in this section ("Compile incremental", "Elaborate incremental", "Simulate", "Clean snapshot and pack files" and "Compile VerilogA as Verilog-AMS" are unchecked).

    - SIMULATION MODE: default selected "Batch (normal)".

    -SAVE AND RESTART OPTIONS: Nothing set nor selected.

    By the way, in the past, one method that worked to me for avoiding compile Verilog/SV views when I netlisted in ADE-L, was to unload the incisive module before opening Virtuoso, then a lot of warnings/errors appeared in the CIW when I netlisted but the netlist process was very fast and the it was correctly generated if there was not netlist errors.

    Other thing I have tried, but not worked, was to set to the "vmsNcvlogExecutable" a fake path/name for ncvlog but the netlist is still compiling and it seems that was only affecting to the compiling process when you close a Verilog/SV view after editing (and then the view could not be closed. that was a really mess, a lot of windows open and they could not be closed because the compiling error).


    Thanks.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information