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How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?

iguerra

Hi,

I would like to know if is possible to avoid compiling the Verilog/sytemVerilog views every time you generate an AMS netlist in ADE-L (based on a config file with a sytemVerilog template).

The compilation time is extremely long and I only want  to confirm if there is no netlist errors (no simulating).

Thanks.

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  • iguerra

    Hi Andrew,

    The version I am using is ICADV12.3. In the sections of the "Netlist and Run Options" I have:

    - NETLIST AND RUN MODE: selected "Cellview-based netlister with ncvlog, ncelab, nsim".

    - RUN OPTIONS: intentionally with the hope to avoid compiling, I have deselected ALL the check boxes in this section ("Compile incremental", "Elaborate incremental", "Simulate", "Clean snapshot and pack files" and "Compile VerilogA as Verilog-AMS" are unchecked).

    - SIMULATION MODE: default selected "Batch (normal)".

    -SAVE AND RESTART OPTIONS: Nothing set nor selected.

    By the way, in the past, one method that worked to me for avoiding compile Verilog/SV views when I netlisted in ADE-L, was to unload the incisive module before opening Virtuoso, then a lot of warnings/errors appeared in the CIW when I netlisted but the netlist process was very fast and the it was correctly generated if there was not netlist errors.

    Other thing I have tried, but not worked, was to set to the "vmsNcvlogExecutable" a fake path/name for ncvlog but the netlist is still compiling and it seems that was only affecting to the compiling process when you close a Verilog/SV view after editing (and then the view could not be closed. that was a really mess, a lot of windows open and they could not be closed because the compiling error).


    Thanks.

Reply
  • iguerra

    Hi Andrew,

    The version I am using is ICADV12.3. In the sections of the "Netlist and Run Options" I have:

    - NETLIST AND RUN MODE: selected "Cellview-based netlister with ncvlog, ncelab, nsim".

    - RUN OPTIONS: intentionally with the hope to avoid compiling, I have deselected ALL the check boxes in this section ("Compile incremental", "Elaborate incremental", "Simulate", "Clean snapshot and pack files" and "Compile VerilogA as Verilog-AMS" are unchecked).

    - SIMULATION MODE: default selected "Batch (normal)".

    -SAVE AND RESTART OPTIONS: Nothing set nor selected.

    By the way, in the past, one method that worked to me for avoiding compile Verilog/SV views when I netlisted in ADE-L, was to unload the incisive module before opening Virtuoso, then a lot of warnings/errors appeared in the CIW when I netlisted but the netlist process was very fast and the it was correctly generated if there was not netlist errors.

    Other thing I have tried, but not worked, was to set to the "vmsNcvlogExecutable" a fake path/name for ncvlog but the netlist is still compiling and it seems that was only affecting to the compiling process when you close a Verilog/SV view after editing (and then the view could not be closed. that was a really mess, a lot of windows open and they could not be closed because the compiling error).


    Thanks.

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