VerilogA vs. built-in device models

Hello, 

I've been using verilog-A to model devices for quite sometime and I wanted to ask what differences are there between the user define model (written in verilogA) and a built-in mosfet model, for example, from the simulator's perspective. 

For example, I have a kit with its specific devices and their models are written in .scs file. Those files simply include the parameters passed to the model equations, I assume, that are hard coded in the simulator. On the other hand, when I write the verilogA code I define both the equations and the model parameters. 

Does the simulator interpret both models the same way in terms of the numerical algorithms used (Newton-Raphson, ..etc)?

Does the simulator process the verilogA equations directly or there is some intermediate step to translate the verilogA code to another form then start solving the equations? (something like a synthesizer in digital). The reason why I am asking this question is that I read some articles about verilogA and they recommended not to overuse the verilogA functions such as ddt , for instance, to ensure proper convergence. So, it sounds to me like there is some intermediate interpretation step done by the simulator before solving the equations. 

Thanks