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detecting process corner from within verilogA model

Hello,

I need to create a model of a current source in verilogA but the value of the current depends also on the process corner. Is there a way for the verilogA model to detect what corner the simulation runs with? In ADEL we specify the corners through an include statement like this:

include <model file> section=typical

Thanks

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Andrew Beckett over 7 years ago

I would suggest you have a parameter that is set in the corners (i.e. a global variable), and then pass that as an instance parameter to your Verilog-A model.

Andrew.
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Andrew Beckett over 7 years ago

I would suggest you have a parameter that is set in the corners (i.e. a global variable), and then pass that as an instance parameter to your Verilog-A model.

Andrew.
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