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  3. detecting process corner from within verilogA model

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detecting process corner from within verilogA model

SoniaMK
SoniaMK over 7 years ago

Hello,

I need to create a model of a current source in verilogA but the value of the current depends also on the process corner. Is there a way for the verilogA model to detect what corner the simulation runs with? In ADEL we specify the corners through an include statement like this:

include <model file> section=typical

Thanks

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  • ElZorro
    ElZorro over 7 years ago

    Thank you, I am following this thread because I need to implement the same and I have a question.

    I have created a file called "wrapper.scs" which looks exaclty like this:

    library wrapper
    section NN
    parameters corner=1
    include "gpdk.scs" section=NN
    endsection NN

    section FF
    parameters corner=2
    include "gpdk.scs" section=FF
    endsection FF

    endlibrary wrapper

    In ADE-L I select Setup/Model-Libraries/
    then I select the path to the model file "wrapper.scs" and I can select between the two sections "NN" and "FF" (the original file gpdk.scs has more sections). So this part is working fine.

    My question is how to read the value of the parameter "corner" into the veriloga model. I am lost here.

    Thank you very much!

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  • Saloni Chhabra
    Saloni Chhabra over 7 years ago in reply to ElZorro

    You can create a parameter in your veriloga model e.g. parameter real getcorner = 1; .  Based on the value of of 'getcorner', you can code the functionality in verilogA model using if/else.

    Then when you instantiate the model, you can pass it the value of 'corner' (coming from models) as:

     I0 (x y z) cellA getcorner=corner

    ahdl_include "/path/to/cellA.va"

    Regards,

    Saloni

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  • ElZorro
    ElZorro over 7 years ago in reply to Saloni Chhabra

    Hi Saloni,

    thank you for your reply.

    Implementing the functionality in the verilogA model using the value of the parameter and if/else is clear.

    My question is how to pass the value from the "wrapper.scs" to the verilogA model?

    This is my file "wrapper.scs":

    library wrapper
    section NN
    parameters corner=1
    include "gpdk.scs" section=NN
    endsection NN

    section FF
    parameters corner=2
    include "gpdk.scs" section=FF
    endsection FF

    endlibrary wrapper

    This is my model "veriloga.va":

    `include "discipline.h"
    `include "constants.h"
    module inv(A, Y);
    input A;
    output Y;
    electrical A, Y;
    parameter real getcorner=1; // how to pass "corner" from "gpdk.scs" to "getcorner" of "veriloga.va" ???

    endmodule

    When I instantiate the verilogA model (cellview name is "veriloga_read_corner") in the schematic testbench I press Q (properties) and set:

    CDF Parameter of view      veriloga_read_corner

    getcorner                            corner

    But I get following error:

    nchelp ncelab CUBSPA
    ncelab/CUBSPA =
    Assigning a string value to a parameter which is declared to be either
    real or integer is illegal.

    In summary, what I am missing is how to pass the parameter value "corner" defined in "wrapper.scs" to the parameter "getcorner" inside the "veriloga.va" model.

    Thank you very much for your help.

     

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  • Saloni Chhabra
    Saloni Chhabra over 7 years ago in reply to ElZorro

    I just tried this on a small testcase and here's what I had to do. When you run netlisting from ADE, do you get a design variable called 'corner' added to the state? You can give the default value to 'corner' in ADE state e.g. 1, and then run the simulation. Spectre will then see variable corner being defined more than once, so depending upon your setup, you might get an error for the same parameter being defined twice. To get past that error, you can set Simulation option redefinedparams=warning. The value coming from models will override the value set in ADE. Hope this helps.

    Regards,
    Saloni

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  • ElZorro
    ElZorro over 7 years ago in reply to Saloni Chhabra

    Thank you again Shaloni.

    Indeed I get the following error:

    ERROR (SFE-59): ".../models/spectre/wrapper.scs" 9: Parameter `corner' was previously defined.
    Please try to add `+spice' in command line or option `redefinedparams' in netlist to avoid these type of errors.

    Following your suggestion I do
    ADE-L/Simulation/Options/Analog/
    Check Tab
    redefinedparams [x] warning /Apply/ok

    and this is working as expected. I can see how the parameter "getcorner" inside the veriogA model takes the value given by parameter "corner" inside the "wrapper.scs" model file.

    Thank you very much for your help! 

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  • ElZorro
    ElZorro over 7 years ago in reply to Saloni Chhabra

    Thank you again Shaloni.

    Indeed I get the following error:

    ERROR (SFE-59): ".../models/spectre/wrapper.scs" 9: Parameter `corner' was previously defined.
    Please try to add `+spice' in command line or option `redefinedparams' in netlist to avoid these type of errors.

    Following your suggestion I do
    ADE-L/Simulation/Options/Analog/
    Check Tab
    redefinedparams [x] warning /Apply/ok

    and this is working as expected. I can see how the parameter "getcorner" inside the veriogA model takes the value given by parameter "corner" inside the "wrapper.scs" model file.

    Thank you very much for your help! 

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