Creating all pin symbol containing inherited power\ground connections

Typically I'd expect the inherited connections to become explicit once layout has been done - effectively you've "hardened" the connections.

It's not clear which inherited connections you're talking about - if it was to the leaf components, I'd expect you to have them connected to real power connections. If it was for the extracted block itself, then it may just be that you haven't got pins on your layout view with the netExpressions on.

Wasn't clear which extraction tool you're using either?

Andrew.

Hello Andrew,

Sorry for not providing the details related to the extraction tool and inherited connections. Let me clarify them first.

The extraction tool I am using, is PLaSMa. Here for extraction I am selecting StarRC. 

Let me explain now the steps I followed. I drew a schematic where I used vdd_inherit, vdd1_inherit, gnd_inherit, gnds_inherit from STlib library. A symbol is generated from the schematic cellview, which I used in the testbench for the testing purpose.

Once the circuit schematic is complete, I drew the layout. In the layout, I used explicit pins for the power rails. Once, the DRC and LVS results are clean, I went for extraction. 

The extracted netlist is used while running the same testbench. I selected the 'extracted' option in ADE for that. Now, I see the simulation result is way too far from the actual output. While debugging, I realised that the extracted netlist cannot find vdd, vdd1 and gnds.

Please let me know whether there are points which I still missed out. 

Regards

Saikat

Saikat,

I don't know what PLaSMa is (never heard of it). However, StarRC is a Synopsys tool, so the problem may be how StarRC is generating its extracted views - you would need to contact Synopsys about that, or ask on one of their forums. If it's not in the extracted netlist, it's probably not in the extracted view either - so most likely the issue is related to how the extracted view is generated.

Regards,

Andrew.

Dear Andrew,

I used Quantus QRC extraction tool as well. The problem was same.

I found the following solution suggested by you.

https://groups.google.com/forum/#!msg/comp.cad.cadence/j9JmVQv2TQY/19ROP1v-Y88J

I tried following the same. However, there are some differences in the options as I am using a different version of the tool. But I am not successful with this.

My final goal is to have a symbol where I will have all the inherited connections as pins, even if the inherited connections are used in the schematic. I have given the following example which I would like to achieve.

Regards

Saikat