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Creating all pin symbol containing inherited power\ground connections

saikatc

Hi,

I am working on Virtuoso, version IC6.1.7-64b.500.4. I am using inherited connections in the schematic. AFter parasitic extraction, I observe that the inherited connections are missing in the netlist. I know that it is not recommended to use inherited netlist. Still, is it possible to have a work around so that with the inherited connections we can have a symbol with all the power\ground pins?

thanks in advance.

Saikat Chatterjee

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  • saikatc

    Hello Andrew,

    Sorry for not providing the details related to the extraction tool and inherited connections. Let me clarify them first.

    The extraction tool I am using, is PLaSMa. Here for extraction I am selecting StarRC. 

    Let me explain now the steps I followed. I drew a schematic where I used vdd_inherit, vdd1_inherit, gnd_inherit, gnds_inherit from STlib library. A symbol is generated from the schematic cellview, which I used in the testbench for the testing purpose.

    Once the circuit schematic is complete, I drew the layout. In the layout, I used explicit pins for the power rails. Once, the DRC and LVS results are clean, I went for extraction. 

    The extracted netlist is used while running the same testbench. I selected the 'extracted' option in ADE for that. Now, I see the simulation result is way too far from the actual output. While debugging, I realised that the extracted netlist cannot find vdd, vdd1 and gnds.

    Please let me know whether there are points which I still missed out. 

    Regards

    Saikat

Reply
  • saikatc

    Hello Andrew,

    Sorry for not providing the details related to the extraction tool and inherited connections. Let me clarify them first.

    The extraction tool I am using, is PLaSMa. Here for extraction I am selecting StarRC. 

    Let me explain now the steps I followed. I drew a schematic where I used vdd_inherit, vdd1_inherit, gnd_inherit, gnds_inherit from STlib library. A symbol is generated from the schematic cellview, which I used in the testbench for the testing purpose.

    Once the circuit schematic is complete, I drew the layout. In the layout, I used explicit pins for the power rails. Once, the DRC and LVS results are clean, I went for extraction. 

    The extracted netlist is used while running the same testbench. I selected the 'extracted' option in ADE for that. Now, I see the simulation result is way too far from the actual output. While debugging, I realised that the extracted netlist cannot find vdd, vdd1 and gnds.

    Please let me know whether there are points which I still missed out. 

    Regards

    Saikat

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