Stats

  • Locked Locked
  • Replies 1
  • Subscribers 126
  • Views 13893
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Abstract generation : Warning : Design contain zero-pin terminal.

Anklon

I'm using Virtuoso Abstract Generator , version  IC6.1.6-64b.500.14 . When trying to run step pins for the cells, I got this warning:

> *WARNING* (ABS-12042): Cell NAND2X1: Design contains zero-pin terminals. There terminals will be deleted.

>INFO (ABS-12001): Cell NAND2X1: There are 5 existing terminals.No pins will be added for them.

>INFO (ABS-11901): Cell NAND2X1: step pin finished.

and pin checking is not successful. I checked the design couple of time and all the pins have proper terminal and pin name. I also generate abstract for INVX0 and INVX1 cells and they work out just fine. 

What could be the possible mistakes here?  How could I solve this? 

Thank You 

Parents
  • Marc Heise

    Hi,

    there is an article in our support database discussing this:

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000005xFqPEAU&pageName=ArticleContent&sq=

    Let me know if you can't access it and I will paste some more of it here.

    Basically it says you have terminals in your layout without a physical pin shape.

    Some parts of the article:

    *************************************************************************************************************************************

    In IC6.1.6 and earlier releases, the warning is coming because there is some net and terminal in layout view for which there is
    no physical pin. This can be verified by interactively opening the layout design in virtuoso and calling below SKILL code in CIW:

    cv=geGetEditCellView()
    cv~>terminals~>pins

    It will show an output similar to below and will have atleast one nil in it.
    \t ((db:0x754fe120)
    \t     (db:0x754fe11e)
    \t     (db:0x754fe123)
    \t     (db:0x754fe122)
    \t     (db:0x754fe11f)
    \t     (db:0x754fe121) nil
    \t )

    It suggests that cellview has logical terminals without any physical pins. To fix such a layout you can interactively call below SKILL
    code after opening the layout in EDIT mode. It will delete such a net and terminal.

    cv=geGetEditCellView()
    foreach(tm cv~>terminals
                    unless(tm~>pins dbDeleteObject(tm~>net))
                    )

    And then save the layout and run a new session of Abstract Generator.

    **************************************************************************************************************************

    Regards,

    Marc

Reply
  • Marc Heise

    Hi,

    there is an article in our support database discussing this:

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000005xFqPEAU&pageName=ArticleContent&sq=

    Let me know if you can't access it and I will paste some more of it here.

    Basically it says you have terminals in your layout without a physical pin shape.

    Some parts of the article:

    *************************************************************************************************************************************

    In IC6.1.6 and earlier releases, the warning is coming because there is some net and terminal in layout view for which there is
    no physical pin. This can be verified by interactively opening the layout design in virtuoso and calling below SKILL code in CIW:

    cv=geGetEditCellView()
    cv~>terminals~>pins

    It will show an output similar to below and will have atleast one nil in it.
    \t ((db:0x754fe120)
    \t     (db:0x754fe11e)
    \t     (db:0x754fe123)
    \t     (db:0x754fe122)
    \t     (db:0x754fe11f)
    \t     (db:0x754fe121) nil
    \t )

    It suggests that cellview has logical terminals without any physical pins. To fix such a layout you can interactively call below SKILL
    code after opening the layout in EDIT mode. It will delete such a net and terminal.

    cv=geGetEditCellView()
    foreach(tm cv~>terminals
                    unless(tm~>pins dbDeleteObject(tm~>net))
                    )

    And then save the layout and run a new session of Abstract Generator.

    **************************************************************************************************************************

    Regards,

    Marc

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.