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VerilogA model Monte Carlo Simulation - Histogram Curve

vijaykpd

Hi,

I want to try monte carlo analysis for circuits defined in veriloga model. So I have started with the  ahdlLib" "res" cell example provided in the cadence support ((Link) . I have done the following steps to replicate the procedure.

  • Modified the verilogA model of "res" cell from ahdlib library as given in the example
module res(vp, vn);

inout vp, vn;

electrical vp, vn;

(* cds_inherited_parameter *) parameter real monteres = 0;

parameter real r = 1k;

localparam real r_effective = r + monteres; // nominal resistance plus

                        // monte-carlo mismatch effect


   analog

      V(vp, vn) <+ (r_effective)*I(vp, vn);


endmodule
  • Created res_mismatch.scs file with the following content      

simulator lang=spectre
global 0

parameters monteres=10
statistics {
mismatch {
vary monteres dist=gauss std=5
      }
}

  • Created schematic with the modified res cell and vdc source
  • Added the model file (res_mismatch.scs) in the ADE L environment  and executed transient simulation. Its working fine. 
     
  • As I want to see how my circuit (vdc connected to res cell) current varies with respect to resistance variations using monte carlo simulation, I setup ADE XL environment and configured the test.
  • Selected the monte carlo sampling and selected the mismatch statistical variation with number of points as 10

Simulation was completed without any error. But I am not able to get any histogram curve or distribution curve. I want to plot the histogram of circuit current variations with respect to resistance mismatch characteristics.

I think, I am missing few more steps. Kindly help me to get it.

Regards,

Vijay

 

  • mschw

    Dear Vijay,

    maybe you have missed that: Since you are performing a transient simulation and you want to get a histogram of the resistor current you need to specify at which point in time you want to 'extract' the current from your transient simulation .

    Kind regards,

    Matthias

  • vijaykpd
    in reply to mschw

    Hello Matthias,

    Thank you very much for the clue. I have tried with DC analysis too, still I am not getting any histogram curve. But looks like I am missing to write expression in the calculator. It would be helpful, If you could give some information/tips about writing the expression in the calculator either for transient simulation or dc simulation

    Regards,

    Vijay

  • Andrew Beckett
    in reply to vijaykpd

    Vijay,

    Not sure what you've tried doing. I've attached a small worked example (open mylib/testbench/adexl and run a simulation). I've got this set on the plotting options to "Auto" and so it will plot a histogram of the output "op" which is set to VDC("/op"). Alternatively you can use the histogram icon to plot histograms with more control if you need it.

    It's not clear whether you're just not getting the variation (not sure why that would be, since it works for me) - you can see that if  you look at the Detail or Detail Transpose view - or whether it's just the plotting of histograms that is your problem.

    Regards,

    Andrew.

    https://community.cadence.com/cfs-file/__key/communityserver-discussions-components-files/38/mcveriloga.tgz

  • vijaykpd
    in reply to Andrew Beckett

    Hello Andrew,

    Your example working like a charm. Thank you very much for your efforts in creating this example.

    Basically I want to do monte carlo analysis for the circuit variables defined in VerilogA model. So I have started with built in example provided in the cadence support. But I have done mistake in defining the output expression. Your example helped me to correct it. 

    Really your are saving lot of man hours for the forum members, especially beginners like me. Big thanks for your reply

    Regards,

    Vijay

  • vijaykpd
    in reply to vijaykpd

    Hello Andrew,

    I understand that this example varies the parameter r with monteres as mismatch parameter (r_effective = r+monteres). We are able to get the histogram for the op by using the expression VDC("/op"). In addition to that I would like to get the histogram of the parameter r_effective. How to get it or what expression we need to use to get the distribution curve of my samples.

    This may be a very basic question, but I couldn't figure it out, Can you please give your suggestions

    Thanks in advance

    Regards,

    Vijay

  • vijaykpd
    in reply to vijaykpd

    Hello Andrew,

    I got it by writing the expression VDC("/op") / IDC("/V1/MINUS")). Please suggest whether we have any other way of plotting it.

    Thanks in advance

    Regards,

    Vijay 

  • Andrew Beckett
    in reply to vijaykpd

    Vijay,

    I first misread what you wanted and so did some screengrabs on how to plot a histogram of the statistical parameters monteres. So I'll show that in case it's useful, then explain how to get a histogram of r_effective.

    Histogram of monteres

    So, first of all you need to save the mismatch parameters (since you're doing a mismatch simulation). Click the "gear" icon next to the Monte Carlo sampling mode (i.e. where you set the number of samples) and turn on saving of mismatch parameters:

     

    Then run the simulation. After running the simulation, you can use the histogram icon in the results pane:

    Then on the resulting form, pick statistical parameters and choose the instance and parameter:

    Histogram of r_effective

    This is probably simpler. Any real variable you have in your VerilogA model gets saved as an operating point parameter. However, in your model you had r_effective defined as a localparam:

    localparam real r_effective = r + monteres; // nominal resistance plus

    So, I suggest removing the word localparam (it's not really needed):

    real r_effective = r + monteres; // nominal resistance plus

    For convenience to set up the outputs, try running a single run sweeps and corners - and then you can use the calculator and pick the OP button to click on the resistor instance, and choose "r_effective" from the list of available parameters. You can add this as an output expression:

    OP("/I0" "r_effective")

    Where /I0 is the instance name of the component in question. Then you'll get a histogram plotted just as you do with your VDC expression.

    Hope that helps!

    Regards,

    Andrew.

  • vijaykpd
    in reply to Andrew Beckett

    Dear Andrew,

    Simple thanks is really not enough for your time and efforts in creating this step by step procedure.

    Your approach is simpler, more generic and applicable to any variable defined in our VerilogA model

    Thank you so much.

    Regards,

    Vijay

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