• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Verilog A to symbol

Stats

  • Locked Locked
  • Replies 19
  • Subscribers 126
  • Views 24258
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verilog A to symbol

Shobhitkareer
Shobhitkareer over 7 years ago

Hi,

Im trying to make symbol using verilog A, the design is actually formed using 3 files; so in the beginning I have included the file using " 'include abd.vams" but while compling it seems that its to able read that file? One of the file is written in verilog-ams.

Am I missing any step?

Thank you in advance

  • Cancel
Parents
  • Shobhitkareer
    Shobhitkareer over 7 years ago

    Hi,

    I know its against forum rules, but I think this question will make more sense here. Please excuse this time.

    But if I have to do monte carlo simulation in this file how should I include the cds_inherited_parameter function, should it be in all the three file for the same parameter or including cds parameter in file L1 will be sufficient?

    Thank you

    warmest regards

    shobhit

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Shobhitkareer
    Shobhitkareer over 7 years ago

    Hi,

    I know its against forum rules, but I think this question will make more sense here. Please excuse this time.

    But if I have to do monte carlo simulation in this file how should I include the cds_inherited_parameter function, should it be in all the three file for the same parameter or including cds parameter in file L1 will be sufficient?

    Thank you

    warmest regards

    shobhit

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
  • Andrew Beckett
    Andrew Beckett over 7 years ago in reply to Shobhitkareer

    I would expect it would be in PCNFET rather than PCNFET_L1, but then again you didn't say what it is you're planning to statistically vary. The example (as you posted it before) had all instance parameters, whereas in this case you'd need at least one global parameter (which ends up being locally varied for mismatch) which is used within the model somewhere. See this article on how to define the parameters within a VerilogA model for Monte Carlo. Perhaps if you explained what you planned to vary, it would be easier to answer?

    Oh, and it would have been better to create a new thread and include a link to the original thread. This thread is already very long and so pity the poor reader who searches and finds this thread for (say) the monte carlo issue and then has to thread through the massive history above...

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information