Verilog A to symbol

Hi,

 It looks to me like the file cannot be found. You can either include the absolute path to the file, 'include <path_to_file>/abd.vams , or you can keep the include statement as it is and use the UNIX env variable CDS_VLOGA_INCLUDE and set it to the absolute path. Launch again virtuoso to make the variable to be taken into account. 

Btw, I'm assuming that the file written in verilog-ams has only analog content. 

Regards,

Dimitra

Thank you Dimitra for your reply and guidance. But when I do this it includes modules from the other file as well. there are four file a.vams(analog), b1.va (port 1, 2,3,4) ; b2.va (port 1, 2,3,4) and b3.va (port 1, 2,3)

b1 includes a.vams

b2 includes a.vams and b1

b3 includes a.vams and b2

i only made symbol of b3.va but it shows the port4 as well which are part of b1 and b2,  while making the symbol.

this is the following error:-

"Netlister: Cannot find terminal 'CoupleNode' on instance 'I0' in lib 'shobhit' cell '1' view 'schematic'."

thank you once again for your time.

Why are you including the VerilogA from other modules in another? I'd assumed (I suspect Dimitra did too) that these were some common `defines or something like that, rather than other module definitions.

It's best, when creating textual views inside a Virtuoso library, to keep each view only having one module (either directly or via `includes). The appropriate netlister would take care of ensuring that all needed cellViews are referenced when the simulator netlist is created.

Regards,

Andrew

Thanks Andrew for the help maybe this thread in the forum further elaborates my problem 

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/31170/creating-a-cntfet-model-in-cadence-using-veriloga

In this she forgot to give path to the definition of the analog file but I have done that.

Please give your valuable suggestion.

Regards

Shobhit 

Shobhit,

No, that doesn't really explain why you are including one module from another module definition and not putting each module in a separate cellView. So you didn't really answer my question - just pointing to somebody else who has added files into a veriloga view (which isn't a supported use model) doesn't explain anything...

Regards,

Andrew.

Greetings Andrew,

I have created separate cellview for each file and then used that file using 'include.

And the above thread I included is because Im trying to do the same thing from the same link.

Im trying to define  a model and generate symbol whose defination is in verilogA.

Regards

Shobhit

I don't see why you think you need to `include one module in another. Why are you doing that?

Regards,

Andrew.

Because each file contains electrical representation of effects such as schottky, transistor resistance etc, b1 contains core model, b2 contains various effects and b3 is the top level definition of the device.

Regards

Shobhit

Hi Shobhit,

If you have three modules - b1, b2, and b3, and b3 instantiates b1 and b2, there is no need to `include the other files to use them.

The spectre netlister will see the hierarchy and make sure all three files are included (via ahdl_include) into the spectre netlist.

Of course, given that you've not shown the code, I'm reliant on guesswork, but given the symptoms you've described it sounds possible that you've done that. If you want a more precise answer, please post the code you're using so we don't have to guess.

You've also not stated any tools, versions or anything like that. Please read the forum guidelines - we all do this in our spare time, and so it's rather frustrating having to go backwards and forwards trying to collect information to clarify the question.

Kindest Regards,

Andrew.

Kindly forgive me for the negligence.

Im using IC 5.1.41

and please find the code below:-

`include "disciplines.vams"
`include "PCNFET_L2.va"

module PCNFET(Drain,Gate,Source,Sub);

// Input variables definitions
parameter real Lch=`L_channel;
parameter real Lgeff = `Lceff;
parameter real Lss=`L_sd;
parameter real Ldd=`L_sd;
parameter real Efi=`Efo;
parameter real Kgate=`Kox;
parameter real Tox=4.0e-9;
parameter real Csub=20.0e-12;
parameter real Ccsd=`Ccsd;
parameter real CoupleRatio=`CoupleRatio;
parameter real Vfbp=0.0;
parameter real Dout=1.0;
parameter real Sout=0.0;
parameter real Pitch=20.0e-9;
parameter real Wgate=`sub_pitch;
parameter real CNTPos=1.0; //not used
parameter real n1=19;
parameter real n2=0;
parameter real tubes=1.0;

// Electrical connections
inout Drain, Gate, Source, Sub;
electrical Drain, Gate, Source, Sub;

electrical int_Drain1, int_Gate1, int_Source1; //For XPCNFET_L2_edge with CNTPos=1
electrical int_Drain0, int_Gate0, int_Source0; //FOR XPCNFET_L2_midd with CNTPos=0

real Cgpar;

//HSPICE uses the 'm' parameter.
//Here, probes are used along with CCCS to multiply all currents.

//Model edge tubes: probe the currents going into 1 instance
branch (Drain, int_Drain1) probe_drain1;
branch (Gate, int_Gate1) probe_gate1;
branch (Source, int_Source1) probe_source1;

PCNFET_L2 #(.Lch(Lch),.Lgeff(Lgeff),.Lss(Lss),.Ldd(Ldd),.Efi(Efi),.Kgate(Kgate),.Tox(Tox),.Csub(Csub),.Ccsd(Ccsd),.CoupleRatio(CoupleRatio),.Vfbp(Vfbp),.Dout(Dout),.Sout(Sout),.GF(min(Wgate/1.0e-12,1.0)),.Pitch(Pitch),.CNTPos(1),.n1(n1),.n2(n2)) XPCNFET_L2_edge (int_Drain1, int_Gate1, int_Source1, Sub, int_Drain1);

//Model the middle tubes: probe the currents going into 1 instance
branch (Drain, int_Drain0) probe_drain0;
branch (Gate, int_Gate0) probe_gate0;
branch (Source, int_Source0) probe_source0;

PCNFET_L2 #(.Lch(Lch),.Lgeff(Lgeff),.Lss(Lss),.Ldd(Ldd),.Efi(Efi),.Kgate(Kgate),.Tox(Tox),.Csub(Csub),.Ccsd(Ccsd),.CoupleRatio(CoupleRatio),.Vfbp(Vfbp),.Dout(Dout),.Sout(Sout),.GF(min(Wgate/1.0e-12,1.0)),.Pitch(Pitch),.CNTPos(0),.n1(n1),.n2(n2)) XPCNFET_L2_midd (int_Drain0, int_Gate0, int_Source0, Sub, int_Drain0);

analog begin

begin // Assign basic parameter
Cgpar = `Ctot*Wgate;
end

//model the other (min(tubes,2)-1) edge tubes with CC-CS
I(Drain, Sub) <+ (min(tubes,2)-1)*I(probe_drain1);
I(Gate, Sub) <+ (min(tubes,2)-1)*I(probe_gate1);
I(Source, Sub) <+ (min(tubes,2)-1)*I(probe_source1);
//By KCL, the current on node Sub is also scaled automatically

//model the other (max(tubes-2,0)-1) middle tubes with CC-CS:
I(Drain, Sub) <+ (max(tubes-2,0)-1)*I(probe_drain0);
I(Gate, Sub) <+ (max(tubes-2,0)-1)*I(probe_gate0);
I(Source, Sub) <+ (max(tubes-2,0)-1)*I(probe_source0);
//By KCL, the current on node Sub is also scaled automatically

// Placing component
// Capacitors
I(Gate,Sub) <+ ddt(Cgpar*V(Gate,Sub));

end // End: analog begin
endmodule 

thank you for your time and patience Andrew

Regards

Shobhit

Referred from:-

nano.stanford.edu/stanford-cnfet-model-verilog