Verilog A to symbol

Hi,

 It looks to me like the file cannot be found. You can either include the absolute path to the file, 'include <path_to_file>/abd.vams , or you can keep the include statement as it is and use the UNIX env variable CDS_VLOGA_INCLUDE and set it to the absolute path. Launch again virtuoso to make the variable to be taken into account. 

Btw, I'm assuming that the file written in verilog-ams has only analog content. 

Regards,

Dimitra

Thank you Dimitra for your reply and guidance. But when I do this it includes modules from the other file as well. there are four file a.vams(analog), b1.va (port 1, 2,3,4) ; b2.va (port 1, 2,3,4) and b3.va (port 1, 2,3)

b1 includes a.vams

b2 includes a.vams and b1

b3 includes a.vams and b2

i only made symbol of b3.va but it shows the port4 as well which are part of b1 and b2,  while making the symbol.

this is the following error:-

"Netlister: Cannot find terminal 'CoupleNode' on instance 'I0' in lib 'shobhit' cell '1' view 'schematic'."

thank you once again for your time.

Why are you including the VerilogA from other modules in another? I'd assumed (I suspect Dimitra did too) that these were some common `defines or something like that, rather than other module definitions.

It's best, when creating textual views inside a Virtuoso library, to keep each view only having one module (either directly or via `includes). The appropriate netlister would take care of ensuring that all needed cellViews are referenced when the simulator netlist is created.

Regards,

Andrew

Thanks Andrew for the help maybe this thread in the forum further elaborates my problem 

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/31170/creating-a-cntfet-model-in-cadence-using-veriloga

In this she forgot to give path to the definition of the analog file but I have done that.

Please give your valuable suggestion.

Regards

Shobhit 

Shobhit,

No, that doesn't really explain why you are including one module from another module definition and not putting each module in a separate cellView. So you didn't really answer my question - just pointing to somebody else who has added files into a veriloga view (which isn't a supported use model) doesn't explain anything...

Regards,

Andrew.

Greetings Andrew,

I have created separate cellview for each file and then used that file using 'include.

And the above thread I included is because Im trying to do the same thing from the same link.

Im trying to define  a model and generate symbol whose defination is in verilogA.

Regards

Shobhit

I don't see why you think you need to `include one module in another. Why are you doing that?

Regards,

Andrew.

I don't see why you think you need to `include one module in another. Why are you doing that?

Regards,

Andrew.

Because each file contains electrical representation of effects such as schottky, transistor resistance etc, b1 contains core model, b2 contains various effects and b3 is the top level definition of the device.

Regards

Shobhit

Hi Shobhit,

If you have three modules - b1, b2, and b3, and b3 instantiates b1 and b2, there is no need to `include the other files to use them.

The spectre netlister will see the hierarchy and make sure all three files are included (via ahdl_include) into the spectre netlist.

Of course, given that you've not shown the code, I'm reliant on guesswork, but given the symptoms you've described it sounds possible that you've done that. If you want a more precise answer, please post the code you're using so we don't have to guess.

You've also not stated any tools, versions or anything like that. Please read the forum guidelines - we all do this in our spare time, and so it's rather frustrating having to go backwards and forwards trying to collect information to clarify the question.

Kindest Regards,

Andrew.

Kindly forgive me for the negligence.

Im using IC 5.1.41

and please find the code below:-

`include "disciplines.vams"
`include "PCNFET_L2.va"

module PCNFET(Drain,Gate,Source,Sub);

// Input variables definitions
parameter real Lch=`L_channel;
parameter real Lgeff = `Lceff;
parameter real Lss=`L_sd;
parameter real Ldd=`L_sd;
parameter real Efi=`Efo;
parameter real Kgate=`Kox;
parameter real Tox=4.0e-9;
parameter real Csub=20.0e-12;
parameter real Ccsd=`Ccsd;
parameter real CoupleRatio=`CoupleRatio;
parameter real Vfbp=0.0;
parameter real Dout=1.0;
parameter real Sout=0.0;
parameter real Pitch=20.0e-9;
parameter real Wgate=`sub_pitch;
parameter real CNTPos=1.0; //not used
parameter real n1=19;
parameter real n2=0;
parameter real tubes=1.0;

// Electrical connections
inout Drain, Gate, Source, Sub;
electrical Drain, Gate, Source, Sub;

electrical int_Drain1, int_Gate1, int_Source1; //For XPCNFET_L2_edge with CNTPos=1
electrical int_Drain0, int_Gate0, int_Source0; //FOR XPCNFET_L2_midd with CNTPos=0

real Cgpar;

//HSPICE uses the 'm' parameter.
//Here, probes are used along with CCCS to multiply all currents.

//Model edge tubes: probe the currents going into 1 instance
branch (Drain, int_Drain1) probe_drain1;
branch (Gate, int_Gate1) probe_gate1;
branch (Source, int_Source1) probe_source1;

PCNFET_L2 #(.Lch(Lch),.Lgeff(Lgeff),.Lss(Lss),.Ldd(Ldd),.Efi(Efi),.Kgate(Kgate),.Tox(Tox),.Csub(Csub),.Ccsd(Ccsd),.CoupleRatio(CoupleRatio),.Vfbp(Vfbp),.Dout(Dout),.Sout(Sout),.GF(min(Wgate/1.0e-12,1.0)),.Pitch(Pitch),.CNTPos(1),.n1(n1),.n2(n2)) XPCNFET_L2_edge (int_Drain1, int_Gate1, int_Source1, Sub, int_Drain1);

//Model the middle tubes: probe the currents going into 1 instance
branch (Drain, int_Drain0) probe_drain0;
branch (Gate, int_Gate0) probe_gate0;
branch (Source, int_Source0) probe_source0;

PCNFET_L2 #(.Lch(Lch),.Lgeff(Lgeff),.Lss(Lss),.Ldd(Ldd),.Efi(Efi),.Kgate(Kgate),.Tox(Tox),.Csub(Csub),.Ccsd(Ccsd),.CoupleRatio(CoupleRatio),.Vfbp(Vfbp),.Dout(Dout),.Sout(Sout),.GF(min(Wgate/1.0e-12,1.0)),.Pitch(Pitch),.CNTPos(0),.n1(n1),.n2(n2)) XPCNFET_L2_midd (int_Drain0, int_Gate0, int_Source0, Sub, int_Drain0);

analog begin

begin // Assign basic parameter
Cgpar = `Ctot*Wgate;
end

//model the other (min(tubes,2)-1) edge tubes with CC-CS
I(Drain, Sub) <+ (min(tubes,2)-1)*I(probe_drain1);
I(Gate, Sub) <+ (min(tubes,2)-1)*I(probe_gate1);
I(Source, Sub) <+ (min(tubes,2)-1)*I(probe_source1);
//By KCL, the current on node Sub is also scaled automatically

//model the other (max(tubes-2,0)-1) middle tubes with CC-CS:
I(Drain, Sub) <+ (max(tubes-2,0)-1)*I(probe_drain0);
I(Gate, Sub) <+ (max(tubes-2,0)-1)*I(probe_gate0);
I(Source, Sub) <+ (max(tubes-2,0)-1)*I(probe_source0);
//By KCL, the current on node Sub is also scaled automatically

// Placing component
// Capacitors
I(Gate,Sub) <+ ddt(Cgpar*V(Gate,Sub));

end // End: analog begin
endmodule 

thank you for your time and patience Andrew

Regards

Shobhit

Referred from:-

nano.stanford.edu/stanford-cnfet-model-verilog

OK, I tried this - admittedly using IC617, but it should be the same in IC5141 (not sure why you need to use such an old version if this is something new... IC5141 came out in 2004, and the very last hotfix was in 2011)

Anyway, what you have to do is set the env var that Dimitra mentioned early in this thread to include the directory where the parameters.vams file is. In my case I did:

setenv CDS_VLOGA_INCLUDE $PWD/nano_model_35

The I created three cellViews:

• PCNFET_L1 : include files left as-is - so the entire content was as it was in the download from Stanford
• PCNFET_L2 : remove the `include "PCNFET_L1.va" but add `include "parameters.vams" instead.
• PCNFET : use the code from the file PCNFET_L3.va, but remove the `include "PCNFET_L2.va" and add `include "parameters.vams" instead

Symbols then get created (and CDF) for each of the three cells, and if I instantiate PCNFET in a schematic and netlist to spectre in ADE, I get (at the bottom of the netlist):

ahdl_include "/export/home/user/support/forum/nano/nanolib/PCNFET_L2/veriloga/veriloga.va"
ahdl_include "/export/home/user/support/forum/nano/nanolib/PCNFET/veriloga/veriloga.va"
ahdl_include "/export/home/user/support/forum/nano/nanolib/PCNFET_L1/veriloga/veriloga.va"

So the netlister automatically includes all the right pieces into the spectre netlist.

So as I said, you should not include the lower modules into the higher modules. There's no need.

Regards,

Andrew.

I know the version is so old that its frustrating to use, anyhow the error is still existing, when I initiate the instance in the schematic it doesnt show CDF parameters. But I still went on to get the netlist from spectre and attached is the error I got.

This the same problem Im facing for a very long time.

Thank you so much Andrew for such prompt replies and valuable guidance.

Warmest Regards

Shobhit

Error found by spectre in `PCNFET', during circuit read-in.
ERROR (SFE-23): "/home/v45960/shobhit/nano_model_35/CNFET/PCNFET/veriloga/veriloga.va" 94: The instance `XPCNFET_L2_edge' is referencing an undefined model or subcircuit, `PCNFET_L2'. Either include the file containing the definition of `PCNFET_L2', or define `PCNFET_L2' before running the simulation.
ERROR (SFE-23): "/home/v45960/shobhit/nano_model_35/CNFET/PCNFET/veriloga/veriloga.va" 101: The instance `XPCNFET_L2_midd' is referencing an undefined model or subcircuit, `PCNFET_L2'. Either include the file containing the definition of `PCNFET_L2', or define `PCNFET_L2' before running the simulation.

I tried this in IC5141 yesterday (admittedly I was using MMSIM11.1 rather than MMSIM7.2 that you were using, but I doubt that makes a difference) and it works fine. I'm using subversion 5.10.41.500.6.151). 

In terms of the CDF parameters being shown, this works fine - you just have to click on the "CDF Parameter of view" cyclic field to show them:

Note that you should check your netlist (Simulation->Netlist->Display and see if you are getting the three ahdl_include lines). If you're not, maybe you're using an old subversion of IC5141 which had a bug? If so, what are you using (type getVersion(t) in the CIW to get the subversion and post it here). Have you removed the include of the lower level modules in the higher level modules?

Regards,

Andrew

even i thought the same and requested my department for an update but the problem persist

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 15.1.0.801.isr17 64bit -- 19 Apr 2017
Copyright (C) 1989-2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: v45960   Host: razr-vm0-093   HostID: 10AC5D78   PID: 98237
Memory  available: 7.4377 GB  physical: 12.4755 GB
Linux   : Red Hat Enterprise Linux Workstation release 6.7 (Santiago)
CPU Type: Intel(R) Xeon(R) CPU E7-8890 v2 @ 2.80GHz
All processors running at 2793.3 MHz
        Socket: Processors
        0:       0
        2:       1
        4:       2
        6:       3
        
System load averages (1min, 5min, 15min) : 3.8 %, 1.5 %, 0.2 %
This is a virtual machine


Simulating `input.scs' on razr-vm0-093 at 11:43:35 AM, Sat May 12, 2018 (process id: 98237).
Current working directory: /home/v45960/simulation/CNFET/1/adexl/results/data/Interactive.0/1/CNFET:1:1/netlist
Command line:
    /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/bin/spectre -64  \
        input.scs +escchars +log ../psf/spectre.out -format psfxl -raw  \
        ../psf +lqtimeout 900 -maxw 5 -maxn 5 -ahdllibdir  \
        /home/v45960/simulation/CNFET/1/adexl/results/data/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB  \
        +logstatus

Loading /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /home/v45960/simulation/CNFET/1/adexl/results/data/Interactive.0/1/CNFET:1:1/netlist/input.scs
Reading file:  /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/spectre/etc/configs/mapsubckt.cfg
Reading file:  /home/v45960/shobhit/nano_model_35/CNFET/PCNFET/veriloga/veriloga.va
Reading file:  /home/v45960/shobhit/nano_model_35/disciplines.vams
Reading file:  /home/v45960/shobhit/nano_model_35/parameters.vams

Warning from spectre during AHDL read-in.
    WARNING (ASL-1): "/home/v45960/shobhit/nano_model_35/disciplines.vams" 95: The Verilog-A engine changed the units of Spectre quantity `Temp' from `C' to `K'. You might have a Verilog-A nature definition or a VHDL-AMS quantity definition of the same name.

Time for NDB Parsing: CPU = 152.977 ms, elapsed = 418.635 ms.
Time accumulated: CPU = 185.971 ms, elapsed = 418.651 ms.
Peak resident memory used = 43.9 Mbytes.


The CPU load for active processors is :
        Spectre  0 (27.5 %)      1 (19.0 %)      2 (35.7 %)      3 (73.2 %)
        Other   
Opening directory /home/v45960/simulation/CNFET/1/adexl/results/data/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB (775)
Created directory /home/v45960/simulation/CNFET/1/adexl/results/data/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/ff87d38f10e2724b96cac480ecd9f677.PCNFET.ahdlcmi/ (775)
Created directory /home/v45960/simulation/CNFET/1/adexl/results/data/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/ff87d38f10e2724b96cac480ecd9f677.PCNFET.ahdlcmi/Linux-64/ (775)
Compiling ahdlcmi module library.
Finished compilation in 1.5 s (elapsed).
Installed compiled interface for PCNFET.

Error found by spectre in `PCNFET', during circuit read-in.
    ERROR (SFE-23): "/home/v45960/shobhit/nano_model_35/CNFET/PCNFET/veriloga/veriloga.va" 94: The instance `XPCNFET_L2_edge' is referencing an undefined model or subcircuit, `PCNFET_L2'. Either include the file containing the definition of `PCNFET_L2', or define `PCNFET_L2' before running the simulation.
    ERROR (SFE-23): "/home/v45960/shobhit/nano_model_35/CNFET/PCNFET/veriloga/veriloga.va" 101: The instance `XPCNFET_L2_midd' is referencing an undefined model or subcircuit, `PCNFET_L2'. Either include the file containing the definition of `PCNFET_L2', or define `PCNFET_L2' before running the simulation.

Reading link:  /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:  /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading link:  /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:  /CMC/tools/cadence/MMSIM15.10.801_lnx86/tools.lnx86/spectre/etc/ahdl/constants.vams
Time for Elaboration: CPU = 78.987 ms, elapsed = 1.58593 s.
Time accumulated: CPU = 265.958 ms, elapsed = 2.00579 s.
Peak resident memory used = 56.4 Mbytes.


Aggregate audit (11:43:37 AM, Sat May 12, 2018):
Time used: CPU = 266 ms, elapsed = 2.01 s, util. = 13.3%.
Time spent in licensing: elapsed = 115 ms, percentage of total = 5.74%.
Peak memory used = 56.6 Mbytes.
Simulation started at: 11:43:35 AM, Sat May 12, 2018, ended at: 11:43:37 AM, Sat May 12, 2018, with elapsed time (wall clock): 2.01 s.
spectre completes with 2 errors, 1 warning, and 0 notices.
spectre terminated prematurely due to fatal error.

version: sub-version  IC6.1.7-64b.500.14

mmsim 15.1

Im not including the lower levels.

Please find the netlist generated. Still the ahdl are not being included.

Regards

shobhit

Hi Shobhit,

You didn't include the netlist. One thought I had was that maybe you've put veriloga in the Stop View List. This is on Setup->Environment (if not using a config view) or it's in the config view itself. You shouldn't have veriloga in the stop list, because that will stop the netlister descending into the hierarchy within the veriloga view, which would omit the ahdl_include for the lower levels.

You need it in the switch list (so that it switches into the veriloga views), but not in the stop list.

Hopefully that's it?

Regards,

Andrew

Hi Andrew,

Yup I think that was the error, although when I opened it, verilogA wasn't in the stop list.

However now its working.

Thank you so much for your valuable time and for your constant efforts.

Warmest regards

shobhit kareer