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How to use a component (VerilogA) within a .scs model file to drive output signals

MT13

Hi,

I have a .scs model file for a digital block. The digital block has some multi-bit (bus) outputs. At the end of the .scs file, there are a bunch of statements to drive the outputs of the blocks:

v1 (demux\<0\> gnd) vsource type=dc dc=0

and this is repeated for each bit of the multi-bit signal.

This model file is added: ADE -> setup -> simulation files --> (added in the definition files category), and the testbench runs successfully.

Instead of driving each bit along, I would like to drive the whole bus (ideally with an analog value that gets translated during simulation). I have a VerilogA analog to digital component (tested and works) that I would like to use to drive that bus, the syntax that I used is:

AD1 (demux\<3\:0\>) adc_4b one=vdd zero=0 num=demux_val

At first the simulation failed complaining that adc_4b is not defined (although the library containing it is added to the library path in the library manager). I added the veriloga (.va) file that defines the component, once to setup--> simulation files --> definition files, and once to setup--> model files, and in both times the simulation fails because of a whole bunch of errors that seem to be VerilogA parsing errors, for example:

ERROR : (SFE - 874) "path" : unexpected quote character "`". Cannot run the simulation because of syntax error.

and so on.

veriloga is added to the switch view and stop view fields in setup --> environment

I am using IC6.1.7-64b.500.16

Thank you in advance

Parents
  • Saloni Chhabra

    You mentioned that 'veriloga is added to the switch view and stop view fields in setup --> environment' : is veriloga the first view name in the switch view list? With the fields setup as below (see snapshot), you should get the veriloga model included automatically by the netlister using ahdl_include command.

    Regards,

    Saloni

  • MT13
    in reply to Saloni Chhabra

    Hi Saloni,

    Thanks for the reply. Quick question, wouldn't this method result in the simulator grabbing a veriloga view for a block that has multiple views (e.g. schematic and veriloga views)? Because eventually I would like to add the digital block with other analog blocks, and for the analog ones I would like to use their spectre views.

    Thanks

Reply
  • MT13
    in reply to Saloni Chhabra

    Hi Saloni,

    Thanks for the reply. Quick question, wouldn't this method result in the simulator grabbing a veriloga view for a block that has multiple views (e.g. schematic and veriloga views)? Because eventually I would like to add the digital block with other analog blocks, and for the analog ones I would like to use their spectre views.

    Thanks

Children
  • Andrew Beckett
    in reply to MT13

    Saloni's suggestion won't work if you are instantiating the veriloga block from your included .scs file - see my response earlier in the thread. If the veriloga block had been instantiated from a schematic, then it would have worked, and if you needed finer control (i.e. different views to use per cell or per instance or per occurrence) then you'd create a config view to allow you to control that rather than with a global view switch list. However, a config view also won't help you if you if you need to instantiate the veriloga block from an include file - you need to add the ahdl_include as I suggested earlier. 

    Unless of course I've completely misunderstood what you said earlier.

    Regards,

    Andrew.

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