Cadence Liberate Characterization Help

Hi Anuradha,

I am also trying to generate .lib files using the Liberate tool. Since you have already gone through the process, can you please help me with one issue?
I have created a netlist from my circuit and used it in liberate to generate .lib file. However, it seems like the generated netlist is not compatible with the liberate or maybe be I am missing something. Have you had a this kind of issue?

Thanks in advance.

Best regards.
Hossain

Hi, can you be more specific about the issue you have ? Does Liberate give errors when reading the netlist ? 

Anuradha

"/home/DREXEL/msh89/ECEC574/ecect680-s2017/LIBERATE_EXAMPLE/MODELS/include_SS.sp", line 7: Warning: Possible reason is that no section is specified when using statement .lib "
From this message, it looks like you did not specify a corner section here.

INFO (LIB-926): The definition of the sub-circuit or model for instance 'MM_i_1' could not be found. Run the following checks in the given sequence: the subcircuit or model is loaded, the first line in the model file is empty or has a comment, and the netlist syntax is correct. If no problem is found in these checks, use the 'define_leafcell' command to define the sub-circuit or model, and rerun Tcl.

This message indicates you may have to use define_leafcell command to declare model for MM_i_1. This is typically required when you use exclusive_model_included and "char -extsim".  

Hi Guangjun,

Out of the curiosity I am asking, I know that "define_arc" command is not mandatory. But in Liberate example folder, the template used for re-characterization of the library (template_rechar_example.tcl) has defined several power/delay arcs for both sequential and combinatorial cells. Is it specifically done to shorten the .lib file content ? 

Let's say for a simple dynamic double edge-triggerd flip-flop (shown below), is automatic arc determination by Liberate  (without define_arc) enough for accurate results ? 

Thanks

Most likely, the template in the example was written out using write_template -verbose command with an existing library. So, what you you see in the template file reflect the existing arcs in the reference library.

In general, automatically generated vectors should be sufficient. you may try this to verify,

1. with define_cell only, ie. no define_arc or define_leakage commands, use -trial option in char_library command

2. do a test run and write out a .lib

3. use read_library <your .lib from the test run>, then write_template -verbose <filename>

4. look through the template to check it all are covered.

Regards,

Guangjun

Mmm..... another interesting thing I noticed was, the templates generated from fairly newer (commercial) cell libraries do not have define_arc definitions.

Btw could you please kindly check the new post (which is more relevant to this thread) I made in this forum:
community.cadence.com/.../re-characterizing-a-tap-less-cell-library-cadence-liberate

Is this a question.

I can not comment without seeing the library and template. If write_template -verbose does not give you a template with define_arc command, then either the tool has a bug, or the reference library does not have a arc.

Dear Guangjun,

Hi, for a double edge triggered sequential cell, how do we indicate that behavior to Liberate ? When I did the characterization as usual, Liberate treats the double edge triggered cell as a single edge trigger one. i.e. when I ran a simulation over a synthesized design using the characterized library, I can see that the data being only captured at negative-edge of the clock. Not at both edges (which is the behavior of the cell as per spice simulation). I also do not see any setup/hold violations in the simulation.

Any explanation for that, or am I missing a certain Liberate command ??

Thanks in advance

Anuradha

Hi Anuradha,

You may have to use the define_arc command for each arc you want to characterise, in such a case. 

Regards,

Guangjun

Dear Guangjun,

I defined the timing arcs for given conditions as follows (setup/hold and clk->Q delays for both clock rise/fals) : 

https://pastebin.com/jXcsqMjW

According to the manual, define_arc only overwrite the automatically determined arcs, so I presume no extra commands. Even with these settings, I still have only data captured at falling edge of the clock. Am I still missing something here ?

Thanks and Regards

Anuradha

have you tried using define_arc?

for ease of debug, you can,

1. only include two define_arc commands for setup, rise/fall;

2. use set_var debug_flow 1x1, or 2x2 to reduce runtime;

3. save the decks for faill as well as pass

4. disable SKI mode, if you enabled it;

5. do not let the tool flatten the netlist---set_var extsim_flatten_netlist=0

6. use -user_arcs_only option in char_library command.

If you any arcs can not be characterized, you should see an warning or error in logfile.

After the run, check the saved deck to verify,

1. are all side pins are biased as expected/required?

2. does the simulated waveform show an expected behavior for both pass/fail? 

3. play with the saved deck, eg. move the input and clock waveform towards and away from each other, to see if the output waveform does change.

Regards,

Guangjun

for ease of debug, you can,

1. only include two define_arc commands for setup, rise/fall;

2. use set_var debug_flow 1x1, or 2x2 to reduce runtime;

3. save the decks for faill as well as pass

4. disable SKI mode, if you enabled it;

5. do not let the tool flatten the netlist---set_var extsim_flatten_netlist=0

6. use -user_arcs_only option in char_library command.

If you any arcs can not be characterized, you should see an warning or error in logfile.

After the run, check the saved deck to verify,

1. are all side pins are biased as expected/required?

2. does the simulated waveform show an expected behavior for both pass/fail? 

3. play with the saved deck, eg. move the input and clock waveform towards and away from each other, to see if the output waveform does change.

Regards,

Guangjun