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  3. Schematic editor bus naming and connections questions.

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Schematic editor bus naming and connections questions.

mhkvy4
mhkvy4 over 7 years ago

I have 2 questions about instantiating multiple instances, the multiplier parameter and bus naming conventions in the Schematic editor. If I want to connect 4 MOSFETs( in parallel), in series, with another set of parallel MOSFETs like in figure A, do I do it using figure B or figure C. (I think it is figure B). If I do instantiate four MOSFETs like in figure 3, for both the top and bottom set, and if I make the connecting net a bus of width 4 bits then I think I get figure D.

1)So if I have this right figure A and B are the same, D and C are the same. Is this wrong? 

2) if i want to declare an array of say 128 identical series resistors, how do I go about it? 

Do I have to make the nets on either side a bus of 128 bits and instantiate resistors with R<127:0>? How do I go about declaring an array of identical parallel resistors? I am guessing for a parallel array I don't make the nets on either side of the R<127:0> into 128 bit buses. 

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  • Marc Heise
    Marc Heise over 7 years ago

    Hi,

    the m parameter is a model parameter, so there might be difference between having four separate devices and one device multiplied by 4 in the model card. Think along shared S/D areas and their cap values.  C and D are identical, yes.

    For series resistor arrays there is the s-parameter which we support. I don't know if your PDK supports this.  As  workaround you can  use the iterated instance method for series connection as well by defining kind of a loop:

    Expression  on the input net:  IN, internal<127:1>

    Device: RES<128:1>

    Expression on the output net: internal<127:1>, OUT

    IN - RES<128> - internal<127> - RES<127> .........RES<1> -  OUT

    Very useful for any kind of chains. (inverter delay line or ringos), just make sure your layout people are aware of that technique. ;)

    If you want them to be parallel, just connect the array to only one net on each side, if you declare a bus, the devices will be separated.

    Kind regards,

    MMarc

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  • Andrew Beckett
    Andrew Beckett over 7 years ago in reply to Marc Heise
    Marc Heise said:
    the m parameter is a model parameter, so there might be difference between having four separate devices and one device multiplied by 4 in the model card. Think along shared S/D areas and their cap values.  C and D are identical, yes.

    One small tweak to what Marc said. A==B and C==D, but all four should be electrically equivalent. The m-factor is handled within the model code, but it should be (unless there's a bug) exactly equivalent to having m devices in parallel. It's more efficient from a simulation perspective, which is why APS (not Spectre, but it is done with APS) collapses parallel devices into a m-factor instead. Note that topologically B and D are different (and hence you might think that A and C are different), but since the middle nodes between the transistors are at the same potential, it doesn't matter electrically if they are physically connected or not. However, if they are separate devices, it's more work for the simulator as there are more nodes, and more equations to be solved - but the end result should be the same (within numerical tolerances).

    So there should not be a difference (other than a small possibility of a numerical difference in the simulator caused by the fact that the matrices are slightly different in the two cases).

    Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 7 years ago in reply to Marc Heise
    Marc Heise said:
    the m parameter is a model parameter, so there might be difference between having four separate devices and one device multiplied by 4 in the model card. Think along shared S/D areas and their cap values.  C and D are identical, yes.

    One small tweak to what Marc said. A==B and C==D, but all four should be electrically equivalent. The m-factor is handled within the model code, but it should be (unless there's a bug) exactly equivalent to having m devices in parallel. It's more efficient from a simulation perspective, which is why APS (not Spectre, but it is done with APS) collapses parallel devices into a m-factor instead. Note that topologically B and D are different (and hence you might think that A and C are different), but since the middle nodes between the transistors are at the same potential, it doesn't matter electrically if they are physically connected or not. However, if they are separate devices, it's more work for the simulator as there are more nodes, and more equations to be solved - but the end result should be the same (within numerical tolerances).

    So there should not be a difference (other than a small possibility of a numerical difference in the simulator caused by the fact that the matrices are slightly different in the two cases).

    Regards,

    Andrew.

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  • mhkvy4
    mhkvy4 over 7 years ago in reply to Andrew Beckett

    Thanks for the reply. I just wanted to know if issues would arise during LVS even if they are electrically equivalent. 

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