transient simulation accuracy

The schematic is as above. 

It's not that clear to me what you're doing. Can you provide the netlist (input.scs) for the different configurations you are simulating? Since I can't see the simulation setup nor all the parameters from the schematic, the input.scs would be much easier.

Andrew.

Hi, Andrew, 

V0 (net02 0) vsource type=pulse val0=1.5 val1=0 period=25e-9 rise=100e-12 \
fall=100e-12 width=11.9e-9
V10 (IN 0) vsource type=pulse val0=1.5 val1=0 period=25e-9 rise=100e-12 \
fall=100e-12 width=11.9e-9
DELAY198 (net07 OUT 0 IN) delay td=1e-12 gain=1
simulatorOptions options reltol=1e-4 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 gmin=1e-12 rforce=1 \

maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=200n errpreset=conservative write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub

Thanks, 

Ruixin

 The question is that whether this varying edge is a static offset in the transient simulation or it will change time-to-time in a more complex schematic ?  When the time strobe or max time step is set, this error will be eliminate. But I am not sure what would be a proper time strobe to correctly get the transient results for DFT. 

Fundamentally this is because the delay line does not force output time steps. You get time steps at places defined by the input source (the simulator places breakpoints at the transitions to ensure the simulator simulates there), but the output changes when there's a timestep. If you look at the time steps by turning the symbols on the traces, you'll see that there's no time step until a reasonable time (certainly more than 1ps - it's something like 200ps for the top edges, and 25ps at the bottom edges). Bear in mind that the lines on the graph are just joining the simulated points - it's the points which are controlled for accuracy, not the lines.

This isn't necessarily inaccuracy - it's just that the simulator has not bothered to take what it deems as unnecessary time points in the simulator. If the circuit is active enough, it will follow the transitions with sufficient accuracy.

In this trivial case (I assume net07 was supposed to be grounded or this was a sub-part of the real netlist), you could force a timestep 1ps after each transition by adding a second source (I just modified V0 above) with the same parameters as V10 but with delay=1p (you can check the time points with symbols=On again).

As for the correct strobe set up for DFT, I can't say without knowing what you are hoping to use in your DFT... . By the way, maxstep is never the right way to control timesteps for a DFT; strobeperiod might be, but it depends on what you're really trying to do.

Regards,

Andrew.

Thanks a lot for your illustration, Andrew. 

The problem I am faced with is that if I insert such a delay cell with 2-3 ps delay before a PFD in the PLL loop, when plotting the closed loop PLL output spectrum by using DFT, I am not sure how much the time strobe value I should set with a fair simulation speed.  So I asked if the simulated points would change if setting time strobe too wide, which may affect DFT results. For the case, I am working at the reference frequency at 50MHz to generate a 400 MHz output. Should I set the time strobe to be around 1 ps for this case ? Or could you suggest me a more robust method to estimate the spurs in PLL design in the cadence tools ? 

Sincerely, 

Ruixin

Thanks a lot for your illustration, Andrew. 

The problem I am faced with is that if I insert such a delay cell with 2-3 ps delay before a PFD in the PLL loop, when plotting the closed loop PLL output spectrum by using DFT, I am not sure how much the time strobe value I should set with a fair simulation speed.  So I asked if the simulated points would change if setting time strobe too wide, which may affect DFT results. For the case, I am working at the reference frequency at 50MHz to generate a 400 MHz output. Should I set the time strobe to be around 1 ps for this case ? Or could you suggest me a more robust method to estimate the spurs in PLL design in the cadence tools ? 

Sincerely, 

Ruixin

Hi Ruixin,

If you insert a 2-3ps delay before the PFD, all that will do is cause the loop to adjust the phase of the VCO so that divided frequency has a phase offset of 2-3ps from the reference frequency. It won't cause spurs - it will just cause the feedback loop to do its job!

In general high frequency interference at the PFD end won't affect the output because of the loop filter, which is designed to reject high frequency variation at the input of the VCO and keep the VCO stable.

So it's unclear to me where these spurs are coming from in your design and what you're trying to achieve. I suggest you speak with your supervisor (I'm assuming you're from an academic institution) and/or you read some books/papers on PLL design to get some better insight?

Regards,

Andrew.

Hi, Andrew, 

Thanks, I agree with your point and it should not generate spurs. I am just trying to find the proper time strobe based on previous my assumption if the time strobe is not set close enough, it may cause spurs at output of PLL ? I am not sure if I am right or wrong. 

Sincerely, 

Ruixin

Hi Ruixin,

I've no idea why you've made that assumption. As I have said numerous times, a lot of this depends on how you're measuring the output spectrum of the PLL. You've not explained that.

Andrew.

Hi, Andrew, 

The block diagram may seem to be like this 

The multi-phase vco feedback one of the phases sequentially every reference cycle back into PFD, and I measure the PLL's output. I am not sure the setup for the time strobe to estimate the spur. 

Sincerely, 

Ruixin