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Generate SDF for custom digital layout

anmos

Hi,

I want to know what is the procedure that I have to follow in order to generate an SDF file from a custom digital layout I made using Virtuoso.
I have the Verilog of the standard cells I used (Clock Buffers, Inverters, etc.) and the .lib for each of the cells. I have also generated the netlist of my digital design from my schematic, using Ncverilog.
Which are the next steps I need to follow?

Thank you in advance for your valuable help!

Kind regards,
anm

  • anmos

    I cannot imagine that this is the very first time that someone is trying to create an SDF file from a custom layout made in Virtuoso. Hasn't anyone tried this before?
    I suspect that what I am asking might be possible in AMS.

  • anmos

    Two other possibilities  I have thought of are:

    a) Use PVS - Quantus QRC in order to extract SPEF files from my design and then use them in order to manually create my SDF file.
    b) Import my Virtuoso layout into Encounter (and not let Encounter do the routing) and then let Encounter create the SDF file (since I have the netlist in Verilog and the .lib files of the digital standard cells).

    Would any of the above options work?

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