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Generate SDF for custom digital layout

anmos

Hi,

I want to know what is the procedure that I have to follow in order to generate an SDF file from a custom digital layout I made using Virtuoso.
I have the Verilog of the standard cells I used (Clock Buffers, Inverters, etc.) and the .lib for each of the cells. I have also generated the netlist of my digital design from my schematic, using Ncverilog.
Which are the next steps I need to follow?

Thank you in advance for your valuable help!

Kind regards,
anm

Parents
  • anmos

    I cannot imagine that this is the very first time that someone is trying to create an SDF file from a custom layout made in Virtuoso. Hasn't anyone tried this before?
    I suspect that what I am asking might be possible in AMS.

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  • anmos

    I cannot imagine that this is the very first time that someone is trying to create an SDF file from a custom layout made in Virtuoso. Hasn't anyone tried this before?
    I suspect that what I am asking might be possible in AMS.

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