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LVS issues with Hierarchy

aarthymani

Hi All, 

    I have big Analog, small digital block. Most of my design is custom based Analog, done with Virtuoso Schematic and Layout. the small digital blocks, i did digital flow, exported gds and verilog netlist, converted it into CDL for LVS comparison. 

   When I tried to run LVS from Virtuoso using PVS , the first time it failed(Missing NMOS and PMOS)  So I had added N-Well surrounding the instance (excluding NMOS), and this time the LVS is clean. 

   But the problem re-occurs when i instantiate this module in new cell, and try  to run LVS from that hierarchy.  I tried flat LVS run as well. Still same error.  My tool details as fllows.  

Digital flow: Genus 16.10, Innovus 16.1

Virtuoso: 6.17, PVS 15.22 

My digital cells Deep-N-Well and i have only single power domain.

Do anyone have any rough idea on where should i debug?  if need any details, let me know. I will try my level best to put as much as possible

Thanks!

Aarthy

Parents
  • Andrew Beckett

    Hi Aarthy,

    Please contact customer support. Being able to see this will make debugging it much easier.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    Hi Aarthy,

    Please contact customer support. Being able to see this will make debugging it much easier.

    Regards,

    Andrew.

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