Stochastic-mismatch model in Verilog-A

Hello cadence community,

I have a question about adding models when trying to set up an MC simulation. I will be clear enough in what i'm doing:

1| I have my Verilog-A model working with no problems in DC and transient simulations. I've understood that I can use the following line of code in Verilog-A to declare a parameter and then call it in an input file:

(*cds_inherited_parameter*)parameter real my_parameter = 0;

2| When I set up my simulation (by using ADE-L or ADE-XL) in "Model Libraries Setup" I add a model file "myfile.scs" where "my_parameter" declared in my Verilog-A model is called:

simulator lang=spectre
parameters my_parameter=0.5
statistics {
            mismatch{
                     vary my_parameter dist=unif N=0.5
                     }
            } 

3| Now, I've understood that "myfile.scs" notation is used for spectre. But I'm trying to use hspice so, I want to create a new file "myfile.sp" and add it to in "Model Libraries Setup" when doing a simulation. I want to call "my_parameter" (and do a process mismatch) which is in my verilog-A model but this time using hspice. How can I do it?

Best Regards,

Esteban