Liberate for library file

Hi Fengye,

When using write_verilog, out pins must have a 'function' attribute. for flip/flops, a 'ff' group must also be created inside the cell section. If these are not auto-created, you have to use the user_data flow when generateing the .lib file.

Regards,

Guangjun

Hi Guangjun,

Thanks a lot for your reply.  The function attribution of my flipflop cell cannot auto-created. For the usage of the user_data, I don't know if I need to prepare a verilog file as a user_data file. Can you give me some suggestions?

Regards,

Fengye

Hi, Guangjun,

Thanks your reply! With my provided define_cell, Liberate can generate some arc, but I don't know if it's all arcs.  The "Liberty specification document", you mean is the Liberate userguide? The logfile will remind removal error,

like "ERROR (LIB-52): The constraint search failed to find a solution within the search range for arc of cell:'balloon_sim_nognd', r_pin:'CK', r_pin dir:'r', pin:'NRESTORE', pin dir:'r', type:'removal_rising rise_constraint' when: (!D * SAVE), GLITCH_PROBE. This cell will be marked as failed and the constraint data will be set to: 1.0 (see constraint_failed_value). To debug, review the saved simulation results for deck: removal_34. Possible causes include: 'constraint_glitch_peak' too small; 'constraint_check_final_state_threshold' too large; estimated search range too small (see constraint_search_bound). Modify the constraint parameters and rerun."

I really appreiate if you can help me look into my problem. I can provide my full test case, 

链接: pan.baidu.com/.../1k-gja8wv_EXsXKhUh8sZGg 提取码: 6hh9 

Regard,

Fengye

Hi Fengye,

Please use the following ftp account to upload your test case. make sure the following data are included,

1. full logic table and pin information

2. model and netlist

3. all tcl scripts.

Liberty specification is followed by all Vendors/STA tools. It is an industry standard, which is not specific to Cadence tools.

Guangjun

Hi Guangejun,

I have upload my test case with the ftp server. If you have time, I hope you can help me look into it.

Regard,

Fengye

Is this a valid arc for this cell?

cell=balloon_sim_nognd, pin=NRESTORE, related_pin=CK, timing_type=removal_rising, when=(!D * !SAVE), rise_constraint

Hi Guangjun,

This is the error  timing arc I have said. I am not sure if it's not valid for the cell.  NRESTORE is low-active and maybe an asynous input pin.  So, I use the write_template to get all the arcs from the incomplete lib file and run agagin with the given arcs, which the above error removal arc is eliminated.

According to the definition, " Removal time for sequential cells is the minimum length of time at which the set or reset signal must remain after the active edge of the clock to ensure correct functioning of the cell. " I don't understant why there are so many arcs.

Regard,

Fengye

Hi Guangjun,

After I set 'NRESTORE' as a Synchronous input, there are still more problems about the arcs. The all arcs generated by Liberate has a possibility of error. If it's true to eliminate some of them.

Regared,

Fengye

Hi Guangjun,

I looked the Liberate manual and find some commands like

"read_library TSMC_balloon_ss_0p99v_125c_ecsm.lib
# set timing check variables
set vital_timing_violation_format "Tviol_edge"
set vital_recrem_violation_format "Rviol_ref_edge"
set vital_timing_info_format "Tinfo_ref_edge"
set vital_recrem_info_format "Rinfo_ref_edge"
# Output a Vital file
write_vital TSMC_balloon_ss_0p99v_125c_ecsm.vhd"

The the vhd file has some reminder about error, you know how this can help me deal this problem.

Thanks a lot!

Regards,

Fengye

Hi Fengue,

You can not simply ignore a failed arc characterisation. 'removal' constraint is like 'hold'. You should ask the designer to clarify whether this arc is valid. If it is, you can save the failed deck and do debug. there are suggestions in the logfile, which should be tried first. You can also save the passsed deck and use them for debug reference.

For the function, you may have to add it yourself, as this cell may not be normal "standard", but a custom digital. the right function can only be provided by the cell designer and the STA digital engineer. You can also use a similar cell as a reference.

Guangjun 

Is this the same library? If so, it is meant to fail, as your library is not complete.

If 'NRESTORE' is NOT Synchronous, then you can not define it as Synchronous.

If 'NRESTORE' is NOT Synchronous, then you can not define it as Synchronous.