Liberate for library file

Hi Fengye,

When using write_verilog, out pins must have a 'function' attribute. for flip/flops, a 'ff' group must also be created inside the cell section. If these are not auto-created, you have to use the user_data flow when generateing the .lib file.

Regards,

Guangjun

Hi Guangjun,

Thanks a lot for your reply.  The function attribution of my flipflop cell cannot auto-created. For the usage of the user_data, I don't know if I need to prepare a verilog file as a user_data file. Can you give me some suggestions?

Regards,

Fengye

Hi Fengye,

The user_data flow can be applied to your .lib creation. You do not necessarily need to work on the Verilog side. As long as your .lib file is complete, the verilog file should be correct.

I do not understand why the function is not auto-generated. This is quite odd. I suspect some of your settings for characterization might not be right. However, without a full test case, I am not able to further comment.

Regards,

Guangjun

Hi Guangjun,

Thanks a lot ! In fact, I don't know how to use "user_data"  to my .lib creation after referencing the Liberate mannual. For other flipflop cell, the function can be auto-created, but for a balloon flipflop, the .lib file cannot be generated completely with the similar template and char.tcl setting. I just give the define_cell instead of all possible arc. So, there isn't fuction attribution in my lib.

When this lib file is used for synthesis, the cell is marked as 'unusable cell'  , I guess  the function or timing arc maybe the reason. I still want to know if there is some tool or commands about checking the correctness of the lib file.

Regards,

Fengye

Hi Fengye,

What is the difference between a balloon flipflop and a normal flipflop? Is this kind of cell supported by Liberty Specification? For custom digital cell, you may have to add some attribute manually, although it is not always the case. This can either be done by a user_data file or set_attribute command. Again, without a full test case, I can not further comment. So, do you have a full test case?

a user_data file has the same syntax as a .lib file. It can be used in write_library command with -user_data option. You can use write_userdata_library command to generate a user_data file and understand the structure. With an existing user_data file, you will be able to add any extra attributes as required.

Regards,

Guangjun

Hi Guangjun,

Thanks for your patience and suggestions. The balloon flipflop has two asynchronous input "SAVE" and "NRESTORE", the other cell has an asynchronous input  "RENT"
define_cell \
-clock { CK } \
-async { RETN } \
-input { D } \
-output { Q } \
-pinlist { CK D RETN Q } \
-delay delay_template_7x7 \
-power power_template_7x7 \
-constraint constraint_template_3x3 \
-mpw mpw_template_3x1 \
memory_sim_nognd

define_cell \
-clock { CK } \
-async { NRESTORE SAVE } \
-input { D } \
-output { Q } \
-pinlist { CK D NRESTORE SAVE Q } \
-delay delay_template_7x7 \
-power power_template_7x7 \
-constraint constraint_template_3x3 \
-mpw mpw_template_3x1 \
balloon_sim_nognd

I don't whether the balloon cell is supported by Liberty. As the user_data， I will understandand and use as you suggested. Except for the synthesis, you know how to check and verify the correctness of the .lib file?

I know you are busy and I don't want to waste your time. I just hope your suggestions when you are in free time.

Regard,

Fengye

Hi Fengye,

I do not see any fundamental differences between the two define_cell commands. What are the differences in terms of logic behavior?

With this define_cell command, do you get all arcs generated/characterized?

Is balloon a unique type of cell that must be modelled differently, or can it be modelled the same way as a normal ff?--- please check the Liberty specification document.

please read the Liberite manual on write_userdata_library command. You can use read_library-->write_userdata_library to generate an example user_data.lib. then, you can added whatever attribute you want to. Alternatively, you may use set_attribute command to do the same.

Liberate does not check the completeness of a library. This can be done by downstream tools, eg. a STA tool. On the other hand, I suggest you look into the logfile and generated .lib to verify if there is any warnings or missing/failed arcs.

If you can provide a full test case(model+netlist+script) + a detailed logic table, I might be able to help you look into it.

Regards,

Guangjun

Hi, Guangjun,

Thanks your reply! With my provided define_cell, Liberate can generate some arc, but I don't know if it's all arcs.  The "Liberty specification document", you mean is the Liberate userguide? The logfile will remind removal error,

like "ERROR (LIB-52): The constraint search failed to find a solution within the search range for arc of cell:'balloon_sim_nognd', r_pin:'CK', r_pin dir:'r', pin:'NRESTORE', pin dir:'r', type:'removal_rising rise_constraint' when: (!D * SAVE), GLITCH_PROBE. This cell will be marked as failed and the constraint data will be set to: 1.0 (see constraint_failed_value). To debug, review the saved simulation results for deck: removal_34. Possible causes include: 'constraint_glitch_peak' too small; 'constraint_check_final_state_threshold' too large; estimated search range too small (see constraint_search_bound). Modify the constraint parameters and rerun."

I really appreiate if you can help me look into my problem. I can provide my full test case, 

链接: pan.baidu.com/.../1k-gja8wv_EXsXKhUh8sZGg 提取码: 6hh9 

Regard,

Fengye

Hi Fengye,

Please use the following ftp account to upload your test case. make sure the following data are included,

1. full logic table and pin information

2. model and netlist

3. all tcl scripts.

Liberty specification is followed by all Vendors/STA tools. It is an industry standard, which is not specific to Cadence tools.

Guangjun

Hi Guangejun,

I have upload my test case with the ftp server. If you have time, I hope you can help me look into it.

Regard,

Fengye

Is this a valid arc for this cell?

cell=balloon_sim_nognd, pin=NRESTORE, related_pin=CK, timing_type=removal_rising, when=(!D * !SAVE), rise_constraint

Is this a valid arc for this cell?

cell=balloon_sim_nognd, pin=NRESTORE, related_pin=CK, timing_type=removal_rising, when=(!D * !SAVE), rise_constraint

Hi Guangjun,

This is the error  timing arc I have said. I am not sure if it's not valid for the cell.  NRESTORE is low-active and maybe an asynous input pin.  So, I use the write_template to get all the arcs from the incomplete lib file and run agagin with the given arcs, which the above error removal arc is eliminated.

According to the definition, " Removal time for sequential cells is the minimum length of time at which the set or reset signal must remain after the active edge of the clock to ensure correct functioning of the cell. " I don't understant why there are so many arcs.

Regard,

Fengye

Hi Guangjun,

After I set 'NRESTORE' as a Synchronous input, there are still more problems about the arcs. The all arcs generated by Liberate has a possibility of error. If it's true to eliminate some of them.

Regared,

Fengye

Hi Guangjun,

I looked the Liberate manual and find some commands like

"read_library TSMC_balloon_ss_0p99v_125c_ecsm.lib
# set timing check variables
set vital_timing_violation_format "Tviol_edge"
set vital_recrem_violation_format "Rviol_ref_edge"
set vital_timing_info_format "Tinfo_ref_edge"
set vital_recrem_info_format "Rinfo_ref_edge"
# Output a Vital file
write_vital TSMC_balloon_ss_0p99v_125c_ecsm.vhd"

The the vhd file has some reminder about error, you know how this can help me deal this problem.

Thanks a lot!

Regards,

Fengye

Hi Fengue,

You can not simply ignore a failed arc characterisation. 'removal' constraint is like 'hold'. You should ask the designer to clarify whether this arc is valid. If it is, you can save the failed deck and do debug. there are suggestions in the logfile, which should be tried first. You can also save the passsed deck and use them for debug reference.

For the function, you may have to add it yourself, as this cell may not be normal "standard", but a custom digital. the right function can only be provided by the cell designer and the STA digital engineer. You can also use a similar cell as a reference.

Guangjun 

Is this the same library? If so, it is meant to fail, as your library is not complete.

If 'NRESTORE' is NOT Synchronous, then you can not define it as Synchronous.

one quick question: does this cell pass characterisation on other corners, eg. TT?

Hi Guangjun,

Thanks for your reply! 'NRESTORE' may be asynchronous.  The error removal arc may be eliminated. Then the lib can be gennated without error, but still with warnning about "write_verilog". This same case can happer at SS,TT FF cornner. 

When the lib without above removal arc is used for synthesis, some warnning shows the balloon cell is unusable. This is the reason I want to analyze the correctness of the lib file.

After you tried that, are the complete lib file generated?

Regard,

Fengye 

Hi Fengye,

I saw the failed arc, but did not try to debug it. It can be very time consuming and may need knowledge about the logic behavior of the cell. In any case, you need to find out if this arc is valid.

It is not clear to me that the "unusable" warning is due to the removed "removal". What synthesis/tool are you talking about? can you get help on why this warning is issued? in general, a missing arc does not always cause problem. 

regards,

Guangjun

Hi, Guangjun,

Thanks again. I really grateful that you spend your precious time help me. Your suggestions have a great influence on me. The synthesis tool is RTL complier. For the imcomplete balloon library, I delete some arcs about from  NRESTORE  to Q,and add function attribution manually. The synthesis can run normally. But I don't know if it will influence the later automatic Place and route. I will debug and analyze the related arcs to see if it's invalid.

Thanks again!

Regard,

Fengye