• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Liberate for library file

Stats

  • Locked Locked
  • Replies 23
  • Subscribers 124
  • Views 23795
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Liberate for library file

fengye
fengye over 6 years ago

Hello, everyone! I have a problem with the usage of Liberate.  The error information is 

*Warning* (write_verilog) : No function written for pin Q of cell balloon_sim_nognd

Then, I look at the verilog file, some information like that 

module balloon_sim_nognd (Q, D, NRESTORE, SAVE, CK);
output Q;
input D, NRESTORE, SAVE, CK;
reg notifier;
wire delayed_D, delayed_NRESTORE, delayed_SAVE, delayed_CK;
// Missing function for pin Q
// Timing

I don't know the reason.

  • Cancel
Parents
  • Guangjun Cao
    Guangjun Cao over 6 years ago

    Hi Fengye,

    When using write_verilog, out pins must have a 'function' attribute. for flip/flops, a 'ff' group must also be created inside the cell section. If these are not auto-created, you have to use the user_data flow when generateing the .lib file.

    Regards,

    Guangjun

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • fengye
    fengye over 6 years ago in reply to Guangjun Cao

    Hi Guangjun,

    Thanks a lot for your reply.  The function attribution of my flipflop cell cannot auto-created. For the usage of the user_data, I don't know if I need to prepare a verilog file as a user_data file. Can you give me some suggestions?

    Regards,

    Fengye

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • fengye
    fengye over 6 years ago in reply to Guangjun Cao

    Hi Guangejun,

    I have upload my test case with the ftp server. If you have time, I hope you can help me look into it.

    Regard,

    Fengye

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Guangjun Cao
    Guangjun Cao over 6 years ago in reply to fengye

    Is this a valid arc for this cell?

    cell=balloon_sim_nognd, pin=NRESTORE, related_pin=CK, timing_type=removal_rising, when=(!D * !SAVE), rise_constraint

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • fengye
    fengye over 6 years ago in reply to Guangjun Cao

    Hi Guangjun,

    This is the error  timing arc I have said. I am not sure if it's not valid for the cell.  NRESTORE is low-active and maybe an asynous input pin.  So, I use the write_template to get all the arcs from the incomplete lib file and run agagin with the given arcs, which the above error removal arc is eliminated.

    According to the definition, " Removal time for sequential cells is the minimum length of time at which the set or reset signal must remain after the active edge of the clock to ensure correct functioning of the cell. " I don't understant why there are so many arcs.

    Regard,

    Fengye

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • fengye
    fengye over 6 years ago in reply to fengye

    Hi Guangjun,

    After I set 'NRESTORE' as a Synchronous input, there are still more problems about the arcs. The all arcs generated by Liberate has a possibility of error. If it's true to eliminate some of them.

    Regared,

    Fengye

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • fengye
    fengye over 6 years ago in reply to fengye

    Hi Guangjun,

    I looked the Liberate manual and find some commands like

    "read_library TSMC_balloon_ss_0p99v_125c_ecsm.lib
    # set timing check variables
    set vital_timing_violation_format "Tviol_edge"
    set vital_recrem_violation_format "Rviol_ref_edge"
    set vital_timing_info_format "Tinfo_ref_edge"
    set vital_recrem_info_format "Rinfo_ref_edge"
    # Output a Vital file
    write_vital TSMC_balloon_ss_0p99v_125c_ecsm.vhd"

    The the vhd file has some reminder about error, you know how this can help me deal this problem.

    Thanks a lot!

    Regards,

    Fengye

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Guangjun Cao
    Guangjun Cao over 6 years ago in reply to fengye

    Hi Fengue,

    You can not simply ignore a failed arc characterisation. 'removal' constraint is like 'hold'. You should ask the designer to clarify whether this arc is valid. If it is, you can save the failed deck and do debug. there are suggestions in the logfile, which should be tried first. You can also save the passsed deck and use them for debug reference.

    For the function, you may have to add it yourself, as this cell may not be normal "standard", but a custom digital. the right function can only be provided by the cell designer and the STA digital engineer. You can also use a similar cell as a reference.

    Guangjun 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Guangjun Cao
    Guangjun Cao over 6 years ago in reply to fengye

    Is this the same library? If so, it is meant to fail, as your library is not complete.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Guangjun Cao
    Guangjun Cao over 6 years ago in reply to fengye

    If 'NRESTORE' is NOT Synchronous, then you can not define it as Synchronous.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Guangjun Cao
    Guangjun Cao over 6 years ago in reply to fengye

    one quick question: does this cell pass characterisation on other corners, eg. TT?

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • fengye
    fengye over 6 years ago in reply to Guangjun Cao

    Hi Guangjun,

    Thanks for your reply! 'NRESTORE' may be asynchronous.  The error removal arc may be eliminated. Then the lib can be gennated without error, but still with warnning about "write_verilog". This same case can happer at SS,TT FF cornner. 

    When the lib without above removal arc is used for synthesis, some warnning shows the balloon cell is unusable. This is the reason I want to analyze the correctness of the lib file.

    After you tried that, are the complete lib file generated?

    Regard,

    Fengye 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • fengye
    fengye over 6 years ago in reply to Guangjun Cao

    Hi Guangjun,

    Thanks for your reply! 'NRESTORE' may be asynchronous.  The error removal arc may be eliminated. Then the lib can be gennated without error, but still with warnning about "write_verilog". This same case can happer at SS,TT FF cornner. 

    When the lib without above removal arc is used for synthesis, some warnning shows the balloon cell is unusable. This is the reason I want to analyze the correctness of the lib file.

    After you tried that, are the complete lib file generated?

    Regard,

    Fengye 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
  • Guangjun Cao
    Guangjun Cao over 6 years ago in reply to fengye

    Hi Fengye,

    I saw the failed arc, but did not try to debug it. It can be very time consuming and may need knowledge about the logic behavior of the cell. In any case, you need to find out if this arc is valid.

    It is not clear to me that the "unusable" warning is due to the removed "removal". What synthesis/tool are you talking about? can you get help on why this warning is issued? in general, a missing arc does not always cause problem. 

    regards,

    Guangjun

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • fengye
    fengye over 6 years ago in reply to Guangjun Cao

    Hi, Guangjun,

    Thanks again. I really grateful that you spend your precious time help me. Your suggestions have a great influence on me. The synthesis tool is RTL complier. For the imcomplete balloon library, I delete some arcs about from  NRESTORE  to Q,and add function attribution manually. The synthesis can run normally. But I don't know if it will influence the later automatic Place and route. I will debug and analyze the related arcs to see if it's invalid.

    Thanks again!

    Regard,

    Fengye

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Guangjun Cao
    Guangjun Cao over 6 years ago in reply to fengye

    Hi Fengye,

    I tried to debug the failed arc. Spice simulation does not show valid transition or expected signal level for  pin=NRESTORE, related_pin=CK, timing_type=removal_rising, when=(!D * !SAVE), rise_constraint. If the cell is designed correctly, then this is not a valid arc. However, it is designer who can tell. If an auto-generated arc is invalid, you can still use the auto-generation flow, but add define_arc -ignore in the template, eg,

    define_cell \
    -clock { CK } \
    -async { SAVE NRESTORE } \
    -input { D } \
    -output { Q } \
    -pinlist { CK D SAVE NRESTORE Q } \
    -delay delay_template_7x7 \
    -power power_template_7x7 \
    -constraint constraint_template_3x3 \
    -mpw mpw_template_3x1 \
    balloon_sim_nognd

    define_arc \
    -type hold \
    -when "!D * SAVE" \
    -pin NRESTORE \
    -related_pin CK \
    -vector {RxxRx} \       ;#mtach the order to -pinlist

    -ignore \
    balloon_sim_nognd

    -----------------------------------------------------------------

    Is this a retention cell with balloon latch? Please refer to this link for syntax of such cells. You may search for "balloon" to find related information. In particular, there is an example on p.485.

    https://media.c3d2.de/mgoblin_media/media_entries/659/Liberty_User_Guides_and_Reference_Manual_Suite_Version_2017.06.pdf

    According to Liberate manual, the ff/latch group for retention cells have to be added by user. This can be done with -user_data option in write_library command. I believe you already know by now how to use the user_data flow.

    one important note: when you use user_data during write_library, you may want to change setting for cell_use_both_ff_latch_groups, eg setting it to 2.

    Looking through your script, there are two incorrect settings for power/ground, which should be,

    set_gnd -type pwell VPW 0
    set_vdd -type nwell VNW 0.99

    Regards,

    Guangjun

    • Cancel
    • Vote Up +1 Vote Down
    • Cancel
  • fengye
    fengye over 6 years ago in reply to Guangjun Cao

    Hi, Guangjun,

    I really appreciate your solutions. Your reply is so detailed. With you suggestion and the documment you provided, I think I can get final solution about the characterization of the retention cell.

    Thanks again!

    Regard,

    Fengye

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information