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Regarding Simulation time in nc-verilog and in ADE-L/XL + AMS

RFStuff

Dear All,

I have a test-bench  (event based only) have the blocks written in verilog and VHDL.

I want to have the test-bench as schematic view. So I have drawn the test-bench in Schematic-Composer.

So, I can run it only through ADE-L + ams.

I want to know whether this way will have same simulation time as that of the run done by using nc-verilog commands in the terminal.

Can anybody please answer my query ?

Kind Regards,

  • The performance of running via ADE is the same as running from the command line (using irun/xrun typically). If you have no analog nodes in the circuit, you'll see in the log file that the spectre solver is started. If there's no analog (no electrical nodes for example), the log file won't show the analog solver is started, and so the speed should essentially be the same as a standalone command-line digital simulation. There is a chance that the elaboration takes a different amount of time if you're comparing against ncverilog (since the flow is slightly different with ncverilog compared with xrun, but the simulation run time itself I would expect to be similar).

    Andrew.

  • What is the problem you are trying to solve ?

    When you say "So I have drawn the test-bench in Schematic-Composer.", does that mean you just imported your Verilog/VHDL as symbols and stitched them together in a testbench or did you replace them with transistor level equivalents ? If you kept everything in Verilog/VHDL then your simulation time will be the same as Andrew explained, assuming your Stimuli is also the same. If you feed your digital blocks with analogLib clock/VDD/VSS then your stimulai becomes Analog, this would obviously slow things down. Last, when you run from ADE, you must add Netlisting time. 

    Riad

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