Liberate : generate lib file for a level shift cell

Hi,

    Did anyone generate the lib file for a level shift with liberate? I don't know how to make some settings.

(1) For the following netlist, 

.SUBCKT ls_cell IN OUT VDDH VDDL VSS
*.PININFO IN:I OUT:O VDDH:B VDDL:B VSS:B
MPM0 A net10 VDDH VDDH P_12_LLRVT W=100e-9 L=200n M=1
MPM1 net10 net10 VDDH VDDH P_12_LLRVT W=100e-9 L=60n M=1
MPM12 net069 net50 VDDH VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM11 net058 net50 net069 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM8 net071 OUT net046 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM7 net50 OUT net071 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM6 net046 OUT net072 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM10 OUT net50 net070 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM5 B A net10 VDDH P_12_LLHVT W=100e-9 L=60n M=1
MPM4 net072 OUT VDDH VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM9 net070 net50 net058 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MNM6 A In_not VSS VSS N_12_LLLVT W=2e-6 L=60n M=1
MNM8 net50 A VSS VSS N_12_LLLVT W=150e-9 L=100n M=1
MNM7 OUT B VSS VSS N_12_LLLVT W=150e-9 L=100n M=1
MNM3 In_not IN VSS VSS N_12_LLLVT W=2e-6 L=60n M=1
MNM5 B IN VSS VSS N_12_LLLVT W=2e-6 L=60n M=1
MPM3 In_not IN VDDL VDDL P_12_LLLVT W=4e-6 L=60n M=1
.ENDS

(2) the template is 

define_template -type delay \
-index_1 {0.008 0.28 } \
-index_2 {0.01 0.3 } \
delay_template_2x2

define_template -type power \
-index_1 {0.008 0.28 } \
-index_2 {0.01 0.3 } \
power_template_2x2

define_cell \
-input { IN } \
-output { OUT } \
-pinlist { IN OUT } \
-delay delay_template_2x2 \
-power power_template_2x2 \
ls_cell

define_leakage -when "IN" ls_cell
define_leakage -when "!IN" ls_cell

# delay arcs from IN => OUT positive_unate combinational
define_arc \
-vector {XX} \
-related_pin IN \
-pin OUT \
ls_cell

# delay arcs from IN => Y positive_unate combinational
define_arc \
-vector {FF} \
-related_pin IN \
-pin OUT \
ls_cell

(3) the multi-voltage 

set VDD_VALUE 1.20
set VDDS_VALUE 0.30

set_vdd VDDH ${VDD_VALUE}
set_vdd VDDL ${VDDS_VALUE}

(4) the error reminding

ERROR (LIB-88): (define_arc): Ignoring arc for cell: 'ls_cell', pin: 'OUT' X, related_pin: 'IN' X, vector: 'XX', pinlist: 'IN OUT' because of one or more invalid values (for example: value 'X' for signal 'OUT'). The valid values for the pin and related_pin are 'R' and 'F'. All other signals can use: '0', '1', 'R', 'F' or 'X'. Correct the Tcl and rerun.

(5) the input_volttage_range, output_voltage_range，how to get these, I need to use userdate to add these attribute.

I hope someone can help me .

Thanks a lot!