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Pad and Pad Frame

jyoti kandpal

can anyone tell how to make pad and pad frame in gpdk 90 nm technology?, and what is the tolerance level for any circuit after post-layout simulation?

Parents
  • Andrew Beckett

    I don't understand your questions (what do you mean by "make pad and pad frame"? I also don't understand what the second question is related to either).

    You're far more likely to get answers to questions if they are clear and provide enough context.

    Regards,

    Andrew.

  • jyoti kandpal
    in reply to Andrew Beckett

    Hello sir, sir, my first question is that I tried to make pad in gpdk 90nm but when I saw in the LSW window there is no pad layer so i ask how to draw pad and pad frame.
    and my second question is how much difference is acceptable between pre-layout and post-layout simulation value? I got a 13% difference between inverter pre-layout and post-layout values. Is this acceptable or not?

Reply
  • jyoti kandpal
    in reply to Andrew Beckett

    Hello sir, sir, my first question is that I tried to make pad in gpdk 90nm but when I saw in the LSW window there is no pad layer so i ask how to draw pad and pad frame.
    and my second question is how much difference is acceptable between pre-layout and post-layout simulation value? I got a 13% difference between inverter pre-layout and post-layout values. Is this acceptable or not?

Children
  • Andrew Beckett
    in reply to jyoti kandpal

    There's a layer called "Bondpad" - if that's what you mean. You may be better off using gpdk45 from http://pdk.cadence.com as this also has a standard cell and IO library and so that may be a better source to find pads (not sure what you mean by "pad frame").

    As for the difference between pre-layout and post-layout, that will depend on the design, how good your layout is, and what is acceptable to you. I can't tell you what is acceptable to you, since I don't know!

    Regards,

    Andrew.

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