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Liberate: Passive Power Calculation

farhan89

I am characterizing some standard cells (NAND, NOR and D Flip-Flop) using cadence liberate (15.1.4). I am using custom Verilog-A models of the transistor. The characterization is successful with accurate delay and leakage power values bit I couldn't understand how passive power is getting calculated. I have following questions that

- Why passive power is in nJ? I believe the tool is integrating the power (for the certain input conditions of the standard cell) over the simulation time. Then essentially passive power is energy ?

- Why passive power is simulation time dependent? For example, I have run characterization for two different simulation time values (simulation time is set in the characterization tcl script) and in both cases the passive power was different while delay and leakage power is same. The change in passive power would also change the dynamic power results in the synthesis tool. How to select this simulation time?

Regards,
Farhan

  • Guangjun Cao

    Hi Farhan,

    First, please use the latest Liberate release for your characterization work.

    You are right, power is the calculated energy.

    What do you mean by "passive power"? is it the hidden power for input pin? 

    You can use "power_info" and "power_info_filename", along with  "extsim_save_passed" and "extsim_deck_dir" to write out and debug the power characterization.

    Regards,

    Guangjun

  • farhan89
    in reply to Guangjun Cao

    Hi Guangjun,

    Thank you for your help.

    Yes, the hidden pin power which is written as passive power in the datasheet generated after characterization.

    Regards,

    Farhan

  • Guangjun Cao
    in reply to farhan89

    Do you have power_tend_match_tran=1 in your settings?

    Guangjun

  • farhan89
    in reply to Guangjun Cao

    No, I don't have any such command in my characterization script.

    Farhan

  • farhan89
    in reply to Guangjun Cao

    Just to be sure that we are talking the same thing, The passive power I believe is the logic gate power consumption for certain input pin conditions. For example for NAND gate, passive power is calculated in these conditions:

    A1/A2 = inputs

    Y = output

    Passive power A1 rising

    when  A2 & Y

    Passive power A1 falling

    when  A2 & Y

    and also for the second pin (A1) when A2 is rising or falling

  • Guangjun Cao
    in reply to farhan89

    I did not realize the datasheet uses a different term for hidden power.

    Your understanding about hidden power is basically correct. There are some settings that controls how hidden-power or power in general is calculated. 

    If the hidden power changes with simulation time, it may be that the circuit has not been fully initialized to a stable state. in some cases, forcing the power_time to the trans_time may help. Or, you may have to check if extra efforts/settings are needed to initialize the circuit. You should be able to find this out from standalone Spectre simulation and waveform, using the saved deck and powe_info_* settings.

    If the hidden power increases linearly with simulation time, it could be that the leakage has not been subtracted. 

    Regards,

    Guangjun

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