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Reading from a file in Verilog-A

Manev

 Dear All,

To simulate the performance of an analog IC  design (using spectre) , I want to "pass" a specific, predefined, sequence of binary data. For this purpose, I have created a "memory" using VerilogA, which outputs bits at each clock cycle. The example bellow is only for 1 bit. The idea is to load the data sequence from a separate file.

// VerilogA for RTL, memory, veriloga

`include "constants.vams"
`include "disciplines.vams"


module memory(clk, out);

input clk;
output out;
electrical out, clk;

parameter real vtrans = 0.45, high =0.9, td = 2p, tr=2p, tf = 2p;


integer fileHandle;
integer decimal_output;
integer captured_data;
integer x;

analog begin

@ (initial_step)
fileHandle = $fopen("~/bit0");
@ (final_step)
$fclose(fileHandle);
@ (cross (V(clk) - vtrans,+1)) begin
decimal_output = $fscanf(fileHandle,"%d", captured_data);
x = ( captured_data > vtrans);
end

V(out) <+ transition( high*x,td, tr, tf );


end

endmodule

The issue is that, after building, I get the following error in the "Parser Error/Warnings" window:

memory.va (/...../memory.va)

ERR741 [30:27]: Digital or unknown system function '$fscanf' found in analog
block.
</...../memory.va> : Failed with errors (1).

Do you have any toughs on this?

Virtuoso version IC6.1.7-64b.500.23

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