Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 12801
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Different output results of a system with adding new circuits

sajjadsabbaghi

Hello everyone,

I had a strange problem regarding my system simulation in Cadence. My Cadence version is IC6.1.4.485. I am working on the simulation of a high-frequency PLL-based Clock and Data Recovery these days. Today, when I simulated the basic system (all blocks are transistor level), everything was ok and my results were good, but when I added some digital circuits that they are nothing to do with the basic system the output of the system changes. It is very strange because the additional circuits are not connected to the basic system. Can anybody guide me to solve my problem?

Thanks. 

Parents

  • You didn't mention which simulator you're using (see the forum guidelines for info on how to write a good question), and you're also using an ancient tool version (I think at least 11 years old). That said, I suspect this is probably just that the additional circuitry is causing there to be more time steps in the analog solver, and those increased time steps could alter the time the takes for the VCO to start up and hence alter the lock time, and even alter how accurately the oscillator simulates. Without more info, it's really hard to be sure - but given that circuit simulators (such as spectre) solve the entire circuit as a whole, with a common tilmestep for the entire circuit, adding non-connected circuitry can still make a difference, especially if you have some kind of adaptive circuit like a PLL. 

    I can't really tell you more though - there's simply not enough to go on here, and I'm having to do a lot of speculating!

    Andrew 

Reply

  • You didn't mention which simulator you're using (see the forum guidelines for info on how to write a good question), and you're also using an ancient tool version (I think at least 11 years old). That said, I suspect this is probably just that the additional circuitry is causing there to be more time steps in the analog solver, and those increased time steps could alter the time the takes for the VCO to start up and hence alter the lock time, and even alter how accurately the oscillator simulates. Without more info, it's really hard to be sure - but given that circuit simulators (such as spectre) solve the entire circuit as a whole, with a common tilmestep for the entire circuit, adding non-connected circuitry can still make a difference, especially if you have some kind of adaptive circuit like a PLL. 

    I can't really tell you more though - there's simply not enough to go on here, and I'm having to do a lot of speculating!

    Andrew 

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.