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Subthreshold Standard Cells Characterization by Liberate

BarPouy

Hi there,

I'm trying to characterize a standard cells library. I'm using tcl-files, based on RAK.

Nwell of cells in this library does not connected to VDD but also to VDDNW, which could have other values, e.g. 0 V. I set the voltages in char_setup file in this way:

set_vdd     -attributes {related_bias_pin VDDNW direction input voltage_name VDD}  VDD  ${VDD}

set_vdd     -type nwell -attributes {pysical_connection device_layer direction input voltage_name VDDNW }  VDDNW  0

set_gnd VSS 0

Please notice, that there is not any pin with the name VDDNW in the cells layout. For LVS of cells I added tapcell, comprising VDD, VDDNW and VSS, to the cell layout.

Characterization starts and aborts very fast without generating any desired results (see below message on the screen).

---------------------------------------------------------------

Starting on grid with 10 cpus
---- Template Generation start ----
---- Template Generation done ----
-- Characterization Summary --
0 warnings
0 errors

Starting on grid with 10 cpus
---- Characterization start ----
---- Characterization done ----
-- Characterization Summary --
0 warnings
0 errors

Starting on grid with 2 cpus
---- Write library start ----
---- Write library done ----
-- Write library Summary --
0 warnings
0 errors
0 monotonicity warnings

Starting on grid with 2 cpus
---- Write CCS library start ----
[5]    Done

--------------------------

The tool messages in the log file just after initialization step:

can't read "VDDNW": no such variable while executing

Question:

1.  For postlayout simulation I generated for each cells (inclusive tapcell) parasitics. Should I do extraction for each cell manually again or Liberate does this job?

   - in cell_list there are only the name of cells (not tapcell)

2. could be the missing of tapcell the reason of characterization abort?

I appreciate any suggestion of you.

Thanks a lot in advance!

BarPouy

Parents

  • Hi BarPouy,

    1. a power pin can not be 0v. so set_vdd xxxx VDDNW xx is wrong. Physically, NWELL is connected to VDD or a non-zero voltage to ensure a reverse biased Nwell/p-sub junction. Are you using thin SOI technology?

    2. if a PG pin does not exist in the cell, but one or more inputs are friven by the non-existence power pin, or if an output is driven by an external power pin, then you can use set_vdd -no_model <netnemae> <value>

    3. I do not understand why you use -attribute. maybe the simple commands can be,

    set_vdd VDD $VDD

    set_vdd -type nwell VDDNW <value> ;# if VDDNW is a port or net name of the cell/netlist

    set_vdd -no_model VDDNW <value> ;# if VDDNW is NOT a port or net name of the cell.

    4. if the tapcell is part of the other cells to ensure expected functionality, then it should be part of the individual netlist. The actual netname can vary in the case of post layout netlist.

    Regards,

    Guangjun  

Reply

  • Hi BarPouy,

    1. a power pin can not be 0v. so set_vdd xxxx VDDNW xx is wrong. Physically, NWELL is connected to VDD or a non-zero voltage to ensure a reverse biased Nwell/p-sub junction. Are you using thin SOI technology?

    2. if a PG pin does not exist in the cell, but one or more inputs are friven by the non-existence power pin, or if an output is driven by an external power pin, then you can use set_vdd -no_model <netnemae> <value>

    3. I do not understand why you use -attribute. maybe the simple commands can be,

    set_vdd VDD $VDD

    set_vdd -type nwell VDDNW <value> ;# if VDDNW is a port or net name of the cell/netlist

    set_vdd -no_model VDDNW <value> ;# if VDDNW is NOT a port or net name of the cell.

    4. if the tapcell is part of the other cells to ensure expected functionality, then it should be part of the individual netlist. The actual netname can vary in the case of post layout netlist.

    Regards,

    Guangjun  

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