Subthreshold Standard Cells Characterization by Liberate

Hi BarPouy,

1. a power pin can not be 0v. so set_vdd xxxx VDDNW xx is wrong. Physically, NWELL is connected to VDD or a non-zero voltage to ensure a reverse biased Nwell/p-sub junction. Are you using thin SOI technology?

2. if a PG pin does not exist in the cell, but one or more inputs are friven by the non-existence power pin, or if an output is driven by an external power pin, then you can use set_vdd -no_model <netnemae> <value>

3. I do not understand why you use -attribute. maybe the simple commands can be,

set_vdd VDD $VDD

set_vdd -type nwell VDDNW <value> ;# if VDDNW is a port or net name of the cell/netlist

set_vdd -no_model VDDNW <value> ;# if VDDNW is NOT a port or net name of the cell.

4. if the tapcell is part of the other cells to ensure expected functionality, then it should be part of the individual netlist. The actual netname can vary in the case of post layout netlist.

Regards,

Guangjun  

5. when there are multiple power supplies, you also need set_pin_vdd command to tell the tool which power supply a pin is associated with.

Hi Guangjun,

Thank you for your prompt reply.

1. you are right, a power pin cannot be 0V. For VDD I don't set 0V, however for Nwell one can do body biasing and set Nwell to a voltage, e.g. higer that VDD (to increase Vth) or lower than VDD (to decrease Vth). I'm not using SOI technology.

2. At the beginning I  used set_vdd VDD $VDD and also set_vdd VDDNW $VDDNW and set_gnd VSS 0. I was not aware of using '-no_model', thanks for your suggestion.

3. Affter causing issue with VDDNW I tried with these two commands from Liberate Doc. VDDNW is the forth device port (in schematic), but not presented in layout. Now I use the command set_vdd -type nwell VDDNW 0

4. tapcell is not part of cells but also a separated cell.

5. muliple supplies could be interessting, e.g. for levelshifter if the circuit uses both low and high voltage. However for a cell with single power supply  I think one could put different values for supply (here VDD) in corner-lists, which I plan to do. However for each 'island' on the chip level there is only one VDD. Please correct me if I'm wrong. Maybe, do you mean I should set_pin_vdd for VDDNW since this is an additional power line? Indeed on the chip top level there should be VSS, VDD and VDDNW lines.

I repeat my question of last post:

1.  For postlayout simulation I generated for each cells (inclusive tapcell) parasitics. Should I do extraction for each cell manually again or Liberate does this job?

   - in cell_list there are only the name of cells (not tapcell)

Just I run characterization with set_vdd -type nwell VDDNW 0 . At least it takes time!

Starting on grid with 10 cpus
---- Template Generation start ----
---- Template Generation done ----
-- Characterization Summary --
2 warnings
117 errors

Starting on grid with 10 cpus
---- Characterization start ----
---- Characterization done ----
-- Characterization Summary --
1 warnings
1 errors

Starting on grid with 2 cpus
---- Write library start ----
---- Write library done ----
-- Write library Summary --
2 warnings
1 errors
0 monotonicity warnings

Starting on grid with 2 cpus
---- Write CCS library start ----
---- Write CCS library done ----
-- Write CCS library Summary --
2 warnings
1 errors
0 monotonicity warnings

Starting on grid with 2 cpus
---- Post-processing start ----

In char.log there is one ERROR (LIB-19): Failed to read file (file=/....... .template.tcl": no such file or directory while executing

All 117 errors are due to the 'permission' of cells layout.oa, which are automatically set to -rw-rw----. Maybe, should it be changed to rwx-rw-r--?

ERROR (LIB-902): Failed to open file '/.../AN2d1.sp' for read. Check directory/file paths and permissions and rerun.

...

There is also a warning:

WARNING (LIB-988): (set_vdd): Vdd 'VDDNW' is driven to 0.0 volts. It is normal for ground nets to be set to 0V. Use the set_gnd command instead of set_vdd to clear this message.

However I want this pin to be selectable for different values, e.g. 0, VDD/2 and VDD for desired speed or leakage performance Maybe the values of differemt VDDNW should be given in corner-list, like VDD?

The same error in write_ccs and write_nldm: Maybe, is this a consequential error?

ERROR (LIB-195): (read_ldb): Unable to read the ldb '/xxx.ldb'. Check whether the specified file path is correct and the required access privileges exist on the file, and rerun.
WARNING (LIB-193): (read_ldb): Future characterization and modelling commands will be skipped because of the previous error.  Correct all Tcl errors and rerun.

I will correct it and report you.

In meantime thanks a lot for your help!

Kind regards

BarPouy

again, you can not set a vdd to "0" using set_vdd. if it is "0", use set_gnd.

1. if the content of tap cell is required for the cell to behave as expected, then it is part of the cell, and should be extracted as part of cell in the post layout netlist. 

2. liberate does not work on layout data (layout.oa), it uses netlist. not sure why this is a question of issue. 

3. yes, different VDDNW values should be handled as different corners.

4.  Failed to read file (file=/....... .template.tcl"-- seems the path/file is not correctly defined in your scripts.

5. the rest does not make sense, since your run fails at the very beginning.

Guangjun

1 & 2. The PWEL/NWEL can be defined like below as Guang suggested. You can ignore the power calculation as well as modeling them in the .lib file like below :

set_vdd -ignore_power -no_model -type pwell VBPW  0.4
set_gnd -ignore_power -no_model -type nwell VBNW  0.2

3. But in order to do this, you should have the well contacts VBPW and VBNW in your extracted RC netlist of the cell. Simply attach a TAPCELL to your individual cell and do PEX !

Anuradha

Hi anurans,

Thank you for your infos. For postlayout simulation I used to generate extracted RC (actually I generated RC+CC). I will repeat it, however with the HSPICE or SPECTRE view.

I have not understood why should power calculation be ignored. I modelled Nwell contact, as Guang suggested, in this way:  set_gnd -type nwell VDDNW (I mean VBNW) 0

However I have to change its value and make it selectable via corner list as e.g. 0, VDD/2 and VDD and generate different .lib with different performances (speed, dyn. and leakage power).

I thought Liberate generates itself the extracted RC netlist. I was confused how can Liberate manage with missing of well contacts in cell layout view. I'm new with Liberate!

Thank you again!

Kind regards

BarPouy

if NWELL has a port(pin) in your cell/subckt, then it is not recommended to ignore the power, not is it recommended to use -no_model. however, if NW is an external pin, you may ignore the power. in theory, -no_model should ignore the power as well, but I am not 100% sure about this.

value of NWELL supply can be represented with a global TCL variabl, eg. $NWELL_voltage. However, if this value can be 0, then using set_vdd for this particular value should be avoided.

about the multiple power, if your cell has multiple supplies, you should use set_pin_vdd/gnd to associate each pin with the right supply. this ensures, a. all input signal created by Liberate will have the right power level, b. all output will reach the expected voltage level(tool will check this for different characterizations), c. all related_power attribute is correct. d. all power are correctly characterized. e. all timing measurement is measure at the right absolute values, based on the defined percentage threshold, eg. delay at 50-50%. mulple power domain is very common in IO cell, apart from level shifter.

Guangjun

Hi Guangjun,

Thank you for your info.

There are in each cell (schematic), as well VDD and VSS as VDDNW (for Nwell) ports, however the later is not included in the layout. As usuall, Tapcell, comprising connections for VDD, VSS and also VDDNW, is placed  in each standard cell row of a dig. core. As anurans suggested, in the extracted  netlist (cell + Tapcell) all 3 ports are presented. Now, how can I interpret internal / external port? Is Nwell port an internal port? I think so!

I've not understood why the power may be ignored at all. Any changes of ADDNW voltage leads to the power change of the cell, e.g. change of leakage power.

I will represent VDDNW in the char_init file, which refers to e.g. 3 values in the corner list (set  VDDNW     $env(C_VDDNW)). In a sub-TCL script, which calls corner scenarios,  set_vdd / set_gnd can be appliedby means of 'if'-condition. What do you think about this approach?

Multiple supply cells: except for VDDNW, which can have different values from VDD, there is only one Supply, i.e. VDD. Refer to this fact, do my cells have multiple supplies?

Thank you for your elaborated explanation of using set_pin_vdd/gnd. You are right, IO cells could operate in multiple power domain (particularly for standard cell library, operating in subthreshold regime).

Kind regards

BarPouy

BarPouy said:

For postlayout simulation I used to generate extracted RC (actually I generated RC+CC). I will repeat it, however with the HSPICE or SPECTRE view.

I have not understood why should power calculation be ignored.

Hi, I have replied to your question based on the experience in standard cell library designing.

> If you want the well power to be added to the library you should not ignore it. But in typical Tap-Less library designs, the well power is omitted as the well contact comes as an external cell. In physical design phase, you include a single well contact for several 100s of standard cells. You can directly use -no_model to omit it from .lib if it is not needed !  Typically standard cell netlists include only RC, not CC. But this depends on your requirement. 

BarPouy said:

I've not understood why the power may be ignored at all. Any changes of ADDNW voltage leads to the power change of the cell, e.g. change of leakage power.

> When you set following :

set_vdd -ignore_power -no_model -type pwell VBPW  0.4
set_gnd -ignore_power -no_model -type nwell VBNW  0.2

It only means, you do not count the power contribution from those pins in your .lib file. However setting those two lines imply that you change the bias point of the NMOS/PMOS devices during the characterization. So whatever the effect you're supposed to see (increase leakage, body effects) will be available in your devices regardless of the exclusion of the pins. 

> If you want to merge let's say the currents through VBPW with VDD, you may use combine_rail option : 

set_vdd -combine_rail -cells {NAND2} -include {VBP} VDD 1.1

I hope this is clear....

Anuradha

Hi anurans

Thank you for your explanation. Now it's clear!

Kind regards

BarPouy