Subthreshold Standard Cells Characterization by Liberate

Hi Guangjun,

Thank you for your prompt reply.

1. you are right, a power pin cannot be 0V. For VDD I don't set 0V, however for Nwell one can do body biasing and set Nwell to a voltage, e.g. higer that VDD (to increase Vth) or lower than VDD (to decrease Vth). I'm not using SOI technology.

2. At the beginning I  used set_vdd VDD $VDD and also set_vdd VDDNW $VDDNW and set_gnd VSS 0. I was not aware of using '-no_model', thanks for your suggestion.

3. Affter causing issue with VDDNW I tried with these two commands from Liberate Doc. VDDNW is the forth device port (in schematic), but not presented in layout. Now I use the command set_vdd -type nwell VDDNW 0

4. tapcell is not part of cells but also a separated cell.

5. muliple supplies could be interessting, e.g. for levelshifter if the circuit uses both low and high voltage. However for a cell with single power supply  I think one could put different values for supply (here VDD) in corner-lists, which I plan to do. However for each 'island' on the chip level there is only one VDD. Please correct me if I'm wrong. Maybe, do you mean I should set_pin_vdd for VDDNW since this is an additional power line? Indeed on the chip top level there should be VSS, VDD and VDDNW lines.

I repeat my question of last post:

1.  For postlayout simulation I generated for each cells (inclusive tapcell) parasitics. Should I do extraction for each cell manually again or Liberate does this job?

   - in cell_list there are only the name of cells (not tapcell)

Just I run characterization with set_vdd -type nwell VDDNW 0 . At least it takes time!

Starting on grid with 10 cpus
---- Template Generation start ----
---- Template Generation done ----
-- Characterization Summary --
2 warnings
117 errors

Starting on grid with 10 cpus
---- Characterization start ----
---- Characterization done ----
-- Characterization Summary --
1 warnings
1 errors

Starting on grid with 2 cpus
---- Write library start ----
---- Write library done ----
-- Write library Summary --
2 warnings
1 errors
0 monotonicity warnings

Starting on grid with 2 cpus
---- Write CCS library start ----
---- Write CCS library done ----
-- Write CCS library Summary --
2 warnings
1 errors
0 monotonicity warnings

Starting on grid with 2 cpus
---- Post-processing start ----

In char.log there is one ERROR (LIB-19): Failed to read file (file=/....... .template.tcl": no such file or directory while executing

All 117 errors are due to the 'permission' of cells layout.oa, which are automatically set to -rw-rw----. Maybe, should it be changed to rwx-rw-r--?

ERROR (LIB-902): Failed to open file '/.../AN2d1.sp' for read. Check directory/file paths and permissions and rerun.

...

There is also a warning:

WARNING (LIB-988): (set_vdd): Vdd 'VDDNW' is driven to 0.0 volts. It is normal for ground nets to be set to 0V. Use the set_gnd command instead of set_vdd to clear this message.

However I want this pin to be selectable for different values, e.g. 0, VDD/2 and VDD for desired speed or leakage performance Maybe the values of differemt VDDNW should be given in corner-list, like VDD?

The same error in write_ccs and write_nldm: Maybe, is this a consequential error?

ERROR (LIB-195): (read_ldb): Unable to read the ldb '/xxx.ldb'. Check whether the specified file path is correct and the required access privileges exist on the file, and rerun.
WARNING (LIB-193): (read_ldb): Future characterization and modelling commands will be skipped because of the previous error.  Correct all Tcl errors and rerun.

I will correct it and report you.

In meantime thanks a lot for your help!

Kind regards

BarPouy

again, you can not set a vdd to "0" using set_vdd. if it is "0", use set_gnd.

1. if the content of tap cell is required for the cell to behave as expected, then it is part of the cell, and should be extracted as part of cell in the post layout netlist. 

2. liberate does not work on layout data (layout.oa), it uses netlist. not sure why this is a question of issue. 

3. yes, different VDDNW values should be handled as different corners.

4.  Failed to read file (file=/....... .template.tcl"-- seems the path/file is not correctly defined in your scripts.

5. the rest does not make sense, since your run fails at the very beginning.

Guangjun

again, you can not set a vdd to "0" using set_vdd. if it is "0", use set_gnd.

1. if the content of tap cell is required for the cell to behave as expected, then it is part of the cell, and should be extracted as part of cell in the post layout netlist. 

2. liberate does not work on layout data (layout.oa), it uses netlist. not sure why this is a question of issue. 

3. yes, different VDDNW values should be handled as different corners.

4.  Failed to read file (file=/....... .template.tcl"-- seems the path/file is not correctly defined in your scripts.

5. the rest does not make sense, since your run fails at the very beginning.

Guangjun