How to simulate the same circuit, but with different input combination

Dear helloIamAndrea,

I am currently working on the design of a routing architecture, and i need to test it under different input combinations. My architecture has 32 digital input, and what i would love to do is to feed the system with all the possibile input combination and simulate each one of it.

I will provide some of my thoughts, but I am not familiar enough with your circuit nor its requirements to even suggest my comments are appropriate. For example, some questions that come to mind include:
1. Does your circuit have components that require an analog simulator?
2. Does your circuit include sequential elements or just combinational logic?
3. Is the behavior of your circuit dependent on the output impedance, transition times or phase relationships of its 5 bit input word (32 combinations)?
4. Is there any potential for crosstalk between the 5 bit input bus lines?

I do not know the answers to these questions, so my comments may not be helpful!

Nonetheless, I might suggest you consider using Assembler to create a test where you excite your circuit with a veriloga based 5 bit A/D converter. The input to your 5 bit A/D converter is defined as a variable ( for example VIN_analog) whose analog value spans the range of 0 to 31 to produce the 32 digital output word combinations. The 32 45 ns transient simulations represent the Assembler corner cases. (The analog input variable VIN_analog is used to create the corner cases). There are many veriloga A/D converter examples, but for your information, I have included the code for a very simple, transient simulation compatible, cell below. I am sure far more complex and clever versions exist. If you do choose to use this code, please include the high voltage simulation option as the analog input appears as a maximum of 31 V (even through it is never directly applied to your circuit). The high voltage option setting may be found in the simulation options panel shown in Figure 1.

-How can i automatize the checking process? As soon as a simulation end, "cadence" should check if the system behaved correctly( eventually telling me if it didn't and for which input combination) and go on with the next one.

Your comment “cadence should check” is a bit confusing to me as it has no knowledge of your circuit’s expected behavior (nor do I!).

If the outputs are just a set of logic levels, perhaps you can include a set of gates in your test bench to verify each output assumes the desired output level for the specific input word applied. If you just want to verify that one of the four bits you mentioned is active at a time, it seems a digital summer might be appropriate to include in your test bench. Of course, you could write either a veriloga block as part of your test bench or create an ocean script to include as an Assembler output to automate the checking process. Without knowledge about your circuit or its constraints, I have no idea which of these options might be possible paths to pursue.

You can find lots of information about Assembler and Explorer on the Cadence on-line support portal. Just as one example:

support.cadence.com/.../ArticleAttachmentPortal

I hope this helps a little helloIamAndrea.

Shawn

Veriloga code for simple 5 bit A/D:

// VerilogA for cw540_local, threebit_ad, veriloga
// VerilogA for simple 6 bit analog to digital converter
// B0 is LSB, B2 is MSB, range of VIN is 0 to 127
// sml from Congyin Shi

`include "constants.vams"
`include "disciplines.vams"

module fivebit_ad(VOUT, VDD, VIN, VSS);
output [4:0] VOUT;
electrical [4:0] VOUT;
input VDD;
electrical VDD;
input VIN;
electrical VIN;
input VSS;
electrical VSS;
integer vin_integer;
parameter td=0p;
parameter trf=10p;
real vss_value, vdd_value;
real out4_value, out3_value, out2_value, out1_value, out0_value;

analog begin

@(initial_step) begin
vss_value = V(VSS); /// grab the time=0 values
vdd_value = V(VDD,VSS);
end

vin_integer = abs(V(VIN,VSS));

out4_value = (vin_integer%32<16) ? vss_value : vdd_value;
out3_value = (vin_integer%16<08) ? vss_value : vdd_value;
out2_value = (vin_integer%08<04) ? vss_value : vdd_value;
out1_value = (vin_integer%04<02) ? vss_value : vdd_value;
out0_value = (vin_integer%02<01) ? vss_value : vdd_value;

V(VOUT[4],VSS)<+transition(out4_value,td,trf);
V(VOUT[3],VSS)<+transition(out3_value,td,trf);
V(VOUT[2],VSS)<+transition(out2_value,td,trf);
V(VOUT[1],VSS)<+transition(out1_value,td,trf);
V(VOUT[0],VSS)<+transition(out0_value,td,trf);

end

endmodule

Another approach for driving digital signals is to use the vector file stimulus on Setup->Simulation Files. Or if you want to sweep a parameter, rather than using a Verilog-A model for an ADC, you could use the bussetp component in this article (one of mine): Creating a component that allows setting a value on a bus in an analog simulation . This has a variable bus-width output (up to a maximum of 31 bits wide), and the value can be a parameter which may be set to a variable and then swept in ADE.

Andrew.

Hello Mr. ShawnLogan, many many thanks for your exaustive answer. I wasn't expecting such an articulated answer and that's why the information i provided in the first post were few.
I can't spoil too much my circuit, but i can tell you that i actually have 32 "1bit" digital input. I don't have a 5 bit wide bus, but rather 32 1 bit input. (those inputs are the outputs of 32 pixels).

in the followings i'm answering your questions:
1) the circuit is fully digital, i don't have any analog parts. I designed the schematic with virtuoso schematic editor L, and simulate it with virtuoso analog design environment XL. In my lab we design both analog and digital integrated circuits and we always used the ade L or XL to simulate both the analog and the digital circuits, eventhough they are on 2 separate designs. Are you telling me that there is a better deisgn enviroment( i.e. assembler) to simulate fully digital circuits?

2) the circuits is mainly composed by combinatorial logics, but there are some sequential blocks.

3) i don't fully get your question, but i can tell you that i am not interested in the output impedance nor phase relationships. The fact is that given a different input combination, the circuit will behave differently, and that's why i have to test its behavior under all the possible input combinations.

4) there is no potential crosstalk at the inputs.

For what concern my idea of "automatization", i think that your "digital summer solution" is a valuable one. But given the high number of combination, i will expect 32!(factorial) simulation and this means that i will have to check manually the digital summer too many times. I am looking for a smart way to avoid checking it manually, and let cadence checks it for me (through a script maybe?). For example if for the first combination the digital summer gives 1 as a output, it means that the system is behaving correclty, if instead it gives a 2 as a results, cadence must flag that combination, so that at the end of the tests i can study why that combination failed.

Again i would like to thanks you.

I don't believe you have 32! simulations if you have a 32-bit bus. That would require 2.6x10³⁵ whereas I think you merely have 2³² combinations, i.e. 4,294,967,296. Even 4 billion simulations is unlikely to be feasible, and certainly not in analog simulation. Even if you were able to get through 140 simulations per second (assuming a lot of parallelism and a lot of simulation resource and licenses), that would take you a year. Clearly 32! would be even less feasible (running 600,000,000,000,000,000 simulations per second would take as long as the age of the universe. I guess your deadline is a bit sooner than that!)

Now, given that the circuit is purely digital, if you're looking to do a functional test then it would make more sense to use Verilog models of the digital logic and then simulate in a gate-level simulator (such as Xcelium) and use a constrained random approach for verification (4 billion variations is likely to take a while, although it might be possible in a reasonable time then). If simulating in ADE, you'd need to choose a reasonable way of giving yourself the confidence that it's OK - potentially using the bussetp approach (you'd need two of them for a 32-bit bus since the max bus width is 31 for bussetp) and produce random samples (maybe using monte carlo) for each variant.

It really depends on what you are really hoping to feasibly test.

Andrew.

thanks Mr. Beckett for the answer. Yes you are right, i don't have 32! combination, but just 2^32....just...  I will take a look at this bussetp approach u mentioned and see if i can make something out of it. i Will probably create a verilogA cell to test the outputs of my system