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  3. Failed to create netlist when simulating extracted view

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Failed to create netlist when simulating extracted view

wgtkan
wgtkan over 5 years ago

Hello,

In simulating extracted view, I get the following error:

The question is where do I set simChecTermMismatchAction to ignore or warning?

ERROR (OSSHNL-912): Netlisting failed because terminal 'vbias' specified in placed master 'whole_chip/nmos_two/symbol'
does not exist in switch master 'whole_chip/nmos_two/calibre'. To continue netlisting, either set
the 'simCheckTermMismatchAction' to 'ignore', or set the
'simCheckTermMismatchAction' to 'warning' and 'nlAction' to 'ignore' for the
missing terminal.

ERROR (OSSHNL-912): Netlisting failed because terminal 'vdd' specified in placed master 'whole_chip/nmos_two/symbol'
does not exist in switch master 'whole_chip/nmos_two/calibre'. To continue netlisting, either set
the 'simCheckTermMismatchAction' to 'ignore', or set the
'simCheckTermMismatchAction' to 'warning' and 'nlAction' to 'ignore' for the
missing terminal.

ERROR (OSSHNL-912): Netlisting failed because terminal 'vneg' specified in placed master 'whole_chip/nmos_two/symbol'
does not exist in switch master 'whole_chip/nmos_two/calibre'. To continue netlisting, either set
the 'simCheckTermMismatchAction' to 'ignore', or set the
'simCheckTermMismatchAction' to 'warning' and 'nlAction' to 'ignore' for the
missing terminal.

ERROR (OSSHNL-912): Netlisting failed because terminal 'vo_neg' specified in placed master 'whole_chip/nmos_two/symbol'
does not exist in switch master 'whole_chip/nmos_two/calibre'. To continue netlisting, either set
the 'simCheckTermMismatchAction' to 'ignore', or set the
'simCheckTermMismatchAction' to 'warning' and 'nlAction' to 'ignore' for the
missing terminal.

ERROR (OSSHNL-912): Netlisting failed because terminal 'vpos' specified in placed master 'whole_chip/nmos_two/symbol'
does not exist in switch master 'whole_chip/nmos_two/calibre'. To continue netlisting, either set
the 'simCheckTermMismatchAction' to 'ignore', or set the
'simCheckTermMismatchAction' to 'warning' and 'nlAction' to 'ignore' for the
missing terminal.

ERROR (OSSHNL-912): Netlisting failed because terminal 'vss' specified in placed master 'whole_chip/nmos_two/symbol'
does not exist in switch master 'whole_chip/nmos_two/calibre'. To continue netlisting, either set
the 'simCheckTermMismatchAction' to 'ignore', or set the
'simCheckTermMismatchAction' to 'warning' and 'nlAction' to 'ignore' for the
missing terminal.

End netlisting Jun 25 01:06:32 2020
ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.
...unsuccessful.

I read the previous question regarding my issue as shown below but couldn't get a clue. 

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/35637/error-during-creating-the-netlist-from-layout-using-45nm-technolgy

Thanks in advance for your help.

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  • Quek
    Quek over 5 years ago

    Hi wgtkan

    You can do it as follows:
    a. Create a text file named ".simrc" in the current working directory

    b. Add the following line in it:
    simCheckTermMismatchAction="ignore"

    Before you use it, you might want to check on why the extracted view does not contain vbias, vdd, vneg, etc terminals. It might be a real issue which should not be ignored.


    Best regards
    Quek

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  • wgtkan
    wgtkan over 5 years ago in reply to Quek

    Hello Quek,

    Thanks for your response. I still get the following error:
    Error found by spectre during circuit read-in.
    ERROR (SFE-23): "input.scs" 2753: The instance `I7' is referencing an undefined model or subcircuit, `nmos_two'. Either include the file containing the definition of `nmos_two', or define `nmos_two' before running the simulation.

    When I click on I7 I see the following:


    // Library name: whole_chip
    // Cell name: tb_nmos_two
    // View name: schematic
    I7 (net11 vdd vo_neg net03 vpos vss) nmos_two
    CL (vo_neg 0) capacitor c=2.5p
    Ibia (vdd net11) isource dc=20u type=dc
    Vss (0 vss) vsource dc=1.8 type=dc
    Vdd (vdd 0) vsource dc=1.8 type=dc
    I1 (net03 vo_neg) iprobe
    Vin (vpos 0) vsource dc=Vcm type=dc
    simulatorOptions options psfversion="1.1.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf
    stb stb start=10 stop=1G probe=I1 localgnd=0 annotate=status
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts where=rawfile
    saveOptions options save=all pwr=all currents=all

    The models are already defined and I am not sure what it is asking.

    Thanks a lot.

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  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to wgtkan

    My guess is that something is totally wrong with the calibre view. It sounds as if it doesn't have any pins at all - and the symbol has 6 pins, all of which were connected on instance I7. Without setting the variable, it's quite rightly complaining about the pin mismatch, and with setting the variable it ignores the error, but probably because there were no pins (and maybe no content?) the calibre view didn't get netlisted, so you have no subckt appearing for nmos_two. Because of that, the poor simulator can't find any reference to the definition of nmos_two.

    So all the variable is doing is masking the real problem - the calibre view is not correct. We can't help much with that as Calibre is a Mentor product and we don't know how you've generated it - but it seems to be incorrect.

    Andrew

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  • wgtkan
    wgtkan over 5 years ago in reply to Andrew Beckett

    Hello Andrew,

    Thanks for guiding me in the right direction. 

    The issue was the Calibre is case sensitive and I have to put the following lines in my rule files:

    SOURCE CASE YES
    LAYOUT CASE YES

    What do you recommend as a physical verification tool besides Assura?

    Thanks a lot.

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  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to wgtkan
    wgtkan said:
    What do you recommend as a physical verification tool besides Assura?

    PVS or Pegasus (depending on the process node).

    Andrew.

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