I am working on a very simple design (basically a CMOS inverter) using Virtuoso IC6.1.5 with AMS C35B4C3 PDK.
I included seven ground pins/pads (for GSG RF probes) that are wired together (labelled "MASSE" on the schematic) :
The corresponding layout of course includes these pads, tied together using metal strips (be forgiving, it's an experimental layout) :
In this configuration, DRC and LVS are passed with no errors, and I can make QRC parasitic extraction without problems
However, I'd like to be able to "separate" these ground pins both on the schematic and layout since, in layout, interconnects between these pins through the metal strips introduce parasitic resistances (at least) and inductances that physically make the different pads non equipotential, especially at RF frequencies.
And I need to be able to identify each of these pins with regards to its location on the layout : for instance, the upper left one is connected to the lower right one through a path that is not the same as the lower left-upper left connection. But the extracted layout does not allow me to tell which pin is what...
I've tried to make these pins distinct by assigning a different name to each of them on the schematic, and naming the electrical connections for correct tapping, but LVS fails since it sees shorts between the pins, and this does not allow me to run the QRC parasitic extraction.
So I do not know how to solve this. It's quite similar problem to the one described here :
but the DK I use does not have metal resistors too, and the post gives no solution.
Thanks in advance for any information or correction.
Given that this is a pretty common requirement, I would suggest you contact AMS to ask them how they support the methodology in their PDK? They may have a different way of doing it.
Thanks for answering. I'll ask AMS today.
But if there's no solution from them, is there a more general solution involving PDK-independent techniques ? I've not been able to figure it out (I was not aware it was a common requirement)...
Many thanks anyway, I'll keep you posted.
I also understand your quandary as the need to simulate an extracted view with knowledge of the specific impedance of individual power and ground nets is something we encounter often.
> ...design kit does not have metal resistors
If the PDK does not have any metal resistors, how can an extracted view include the features of the metal traces to the power and ground nets for use in computing their impedances?
Perhaps there may be some misinterpretation of terms in our discussion? Let me try to be more clear on our approach...
The two methods we use to isolate nets that are “theoretically” the same node voltage (which are basically the same as I will detail) rely on inserting a series connected schematic symbol of a metal resistor of some width and length (typically a square or two) to allow a distinct pin to be assigned to each physical location of a power or ground net (or sometimes a signal). Hence, as an example, there may be 6 to 12 vdd pins all of which have a distinct net name (vdd_1, vdd_2,...). This allows for successful LVS and the capability to include the effect of the distributed impedance of the vdd supply net on circuit performance in an extracted view based netlist simulation.
The second method uses a PDK model of a current probe. In this case, in lieu of instantiating a metal resistor in series schematically with the net(s) of interest, the symbol for a current probe is utilized. Although the use of the current probe does not require one to schematically define the dimensions of a square or two of metal as does a metal resistor, the methodology is basically the same as the foundry PDK “models” the current probe as a metal resistor.
Finally, as a further note, we also use metal resistors to create distinct net names for use in probing specific trace locations of a signal net. A one or two square resistor is connected to a location in a signal net of the layout to define a net (on its unconnected terminal) for easy extracted view probing in extracted view based netlist simulations.
I hope this better explains the methodology we use and the meaning of a “metal resistor” Francois!
Many thanks for your thorough explanation. Makes things much clearer.
Based on your information, I digged a bit deeper around these concepts (which explains my delayed answer).
ShawnLogan said:If the PDK does not have any metal resistors, how can an extracted view include the features of the metal traces to the power and ground nets for use in computing their impedances?
The PDK includes parasitic resistors (presistor), capacitors and inductors, that are used in the extracted view. However, if the cells of these parasitic elements in the AMS library do include a schematic, symbol or auLvs view, they do not have a layout view. This makes impossible for me to generate these schematic elements in the layout... (By the way, presistors are tagged "don't use" in the schematic). And the only resistors from the PDK that can be "layout'ed" are at poly levels.
And no iprobes are included in the PDK
More confusing (to me, at least), when browsing through the Assura extraction rules from the founder (extract.rul), I found some descriptions of metal resistors (METRES) for the four metal layers, but I cannot find any reference to them in the PDK literature I have access to...
I've asked AMS, but I'm still waiting for informations from them.
Anyway, many thanks again for your help, and do not hesitate to point out any of my misunderstandings (I'm quite a newbie to Virtuoso)