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Unable to change diode parameters when importing the CDL netlist

OrangeHalo

Hi all,

I am translating a netlist file to schematic using spiceIn in Virtuoso 617. The netlist is for a standard cell library in TSMC 180nm technology. After importing the netlist, I found that two parameters: diode area and pj is not translated properly. I searched the forum and found some threads, and I added *.DIODEAREA in the netlist. But the area was not changed. Now I have two questions:

  • How to modify the file, so that the diode area and pj in schematic can be changed according to the netlist.
  • In the layout of the cell, there are some width and length. But the netlist only provides area of the cell. How can I fill in the length and width of the diode in the schematic?

Here is a how the diode is defined in the netlist file:


*.DIOAREA
*.DIOPERI

.subckt ANTENNABWP7T I VDD VSS
DI3 VSS I dn 0.2037p
.ends

Here is the translated parameters for the diode:

Thanks in advance.

Best,

OrangeHalo

Parents
  • Quek

    Hi OrangeHalo

    Would you please check if you had already added an appropriate parameter mapping during spiceIn? E.g.

    devSelect := diode dn
    propMatch := dn
    propMap := model area abc

    Please go to "CIW: Tools->CDF->Edit CDF" and replace "abc" with the actual CDF name of "Diode_area" parameter.


    Best regards
    Quek

  • OrangeHalo
    in reply to Quek

    Thank you Quek! It really helped me out. But there is another problem:

    When the schematic and layout of the std cell lib are imported into Virtuoso, the layout size of a diode which is used to fix antenna problem is smaller than the minimum size in the schematic. This will account for LVS problems. How can I change the minimum value in CDF parameter so that I can match the layout to the schematic? Or do you have any other suggestion regarding this problem?

    Here are the figures:

    • Size of the diode in layout (It is a N+/Psub diode, the sizes are labelled as 0.42*0.485):

                

    • Size of diode in schematic editor (As you can see, the minimum length(width) is 450nm, which is larger the 420nm shown in previous figure):

               

    Best,

    OrangeHalo

  • Quek
    in reply to OrangeHalo

    Hi OrangeHalo

    This is a common problem after spice-in. CDL netlists sometimes only provide area/perimeter of diodes but LVS rule deck uses W/L for comparison against the layout. As the W/L of the schematic diodes are still using the default values, there will always be parameter mismatches. For such situations, you will have to modify the W/L of the schematic diodes manually. You can open up schematic properties form of the diode and change L from 450n to 420n.

    Changing CDF is not a good idea as it affect the entire PDK. It is better to just change it in the properties form.


    Best regards
    Quek

  • OrangeHalo
    in reply to Quek

    Hi Quek,

    Thank you for you kind reply. But I cannot change W to 420nm, because the minimum value of L is set to be 450nm. When I change it manually, the CIW shows that "L is below minimum - setting to min". How can I fix this problem?

    Best,

    OrangeHalo

  • Quek
    in reply to OrangeHalo

    Hi OrangeHalo

    Now this is strange. If the min value of L for dioden is 450n, why is the layout diode using 420n? Do you get any DRC errors for the layout of the diode?


    Best regards
    Quek

Reply
  • Quek
    in reply to OrangeHalo

    Hi OrangeHalo

    Now this is strange. If the min value of L for dioden is 450n, why is the layout diode using 420n? Do you get any DRC errors for the layout of the diode?


    Best regards
    Quek

Children
  • OrangeHalo
    in reply to Quek

    Hi Quek,

    There is no DRC error in the layout. Actually according to the design manual, the minimum value of L is even less than 420nm. I just dont know why the minimum L of the diode is set to be 450nm.

    Best,

    OrangeHalo

  • OrangeHalo
    in reply to Quek

    Hi Quek,

    Some update: I managed to solve the problem by uncheck a box named "Hard_constrain". I am trying to find out what does that represent for.

    Best,

    OrangeHalo 

  • Quek
    in reply to OrangeHalo

    Hi OrangeHalo

    That's great. Thanks for the update.

    Best regards
    Quek

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