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.tmpADEDir folder is used for unknown reason in Virtuoso, the path is so long

monglebest

I use Virtuoso IC6.1.8-64b.500.11.

The problem I have is that all the netlist/log files are generated under a 

/home/data/ZZZ_simulation/cXXXXX/YYYTBLib/sim_tx_idac_veriloga_1000BT1_v9_config/maestro/results/maestro/.tmpADEDir_cXXXXX/dc_spectre/simulation/YYYTBLib/sim_tx_idac_wakeup_power_seq_v2/adexl/results/data/Interactive.1/1/PowerWakeUp/netlist/input.scs

This path is so long and also the test bench I am working with is sim_tx_idac_wakeup_power_seq_v2, not sim_tx_idac_veriloga_1000BT1_v9_config.

Making the path name under another test bench is very confusing, what's the method to modify this strange default behavior?

Parents
  • Andrew Beckett

    I moved this into a more sensible forum (it's a technical question about Custom IC Design tools, not feedback questions or suggestions about the forum infrastructure).

    This looks like some contamination between ADE XL and ADE Assembler/Explorer - I've not seen this happen. I did a very quick search and didn't find any similar reports (but I didn't spend that long searching, I'm afraid). You should definitely report this to customer support.

    Andrew.

  • monglebest
    in reply to Andrew Beckett

    Thanks, Andrew. Since it doesn't have any performance impact. And I doubt it will be fixed even if I reported. Re-starting Cadence will resolve the issue.

Reply
  • monglebest
    in reply to Andrew Beckett

    Thanks, Andrew. Since it doesn't have any performance impact. And I doubt it will be fixed even if I reported. Re-starting Cadence will resolve the issue.

Children
  • Andrew Beckett
    in reply to monglebest

    I'm not sure where you get the idea that we only want to fix performance related issues. This should definitely be reported to customer support as it will undoubtedly lead to challenges accessing results if not resolved (I still haven't come across it, but others may have done - we need to track down what is causing it).

    Andrew

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