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ERROR in AMS simulation : "expecting a valid compiler directive [16(IEEE)]"

Dear All,

I have a verilog code portion as below:-

But, when I run I get error as :- ncvlog: *E,EXPCPD ... expecting a valid compiler directive [16(IEEE)]. `#if $NUM_STAGES$ > 2.

Could any body please tell how to fix this issue.

`#if $NUM_STAGES$ > 2
sync_mod i_sync_cell(
.Q(z_o),
.CD(~reset_n_i),
.CP(clk_i),
.D(d_i_sg2),
.SE(1'b0),
.SI(d_i_sg2)
);
`#endif

RFStuff over 4 years ago
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Andrew Beckett over 4 years ago in reply to RFStuff

Belated reply (was a bit busy at the time), but `#if (or indeed `#anything) is not a legal directive in Verilog. No idea why you think it would be - it's not in the IEEE 1364 Language Reference Manual (LRM). There are a number of them which are specified in Clause 19 of the 1364-2001 IEEE standard, but there's no `if (only `ifdef).

I assume you got this from somewhere - perhaps it was a non-standard extension in a specific simulator?

Andrew
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