Ideal ADC model setting in adhllib

Dear Mostafa,

Mostafa A said:

Does anyone know how should I set an ideal ADC in adhllib? Specifically parameters "Vref" and "model".

Did you happen to examine the veriloga for the cell? In the comments at the beginning of the file, it notes:

// INSTANCE parameters
// tdel, trise, tfall = {usual} [s]
// vlogic_high = [V]
// vlogic_low = [V]
// vtrans_clk = clk high to low transition voltage [V]
// vref = voltage that voltage is done with respect to [V]
//
// MODEL parameters
// {none}
//
// This model is ideal in the sense that there is no mismatch modeled.

Hence, my understanding is ref is the range of your analog  input signal. Its default value is set to 1.0 V.  This makes sense to me as the first comparison is made to 1/2 of ref:

@ ( initial_step ) begin
halfref = vref / 2;

I don't think the "model" you refer to is a parameter.

Shawn

Hi Shawn,

Thanks you so much for reply. I don't know how can I see and examine the verilog codes of the component in "adhllib". Could you please let me know how I can do that?

Mostafa

Dear Mostafa,

There are a few ways to view the code. Two are included below to hopefully help you.

1. As shown in Figure 1, you may open the  veriloga code for read from the library manager.

2. If you have instantiated the symbol for the component in a schematic, you can descend into its veriloga view directly by doing a bindkey "e"' and selecting its veriloga view.

Do either or both of these help?

Shawn

Figure 1

Thanks a lot dear Shawn,

The first way did not work me because I don't have "verilog" in "view" part. I only have "symbol (I don't know why)

But doesn't matter because the second way worked. 

Thanks

Mostafa

Dear Mostafa,

Mostafa A said:

The first way did not work me because I don't have "verilog" in "view" part. I only have "symbol (I don't know why)

Hmmm...the veriloga view must be accessible or you would not be able to simulate the circuit containing the instantiation. Might the view in the Library Manager be hidden?

Mostafa A said:

But doesn't matter because the second way worked. 

Great! That is good to read! Thank you for letting us know!

Shawn

Oh, now I can see the "verilogA" in "view" part!!! I don't know what happened, I just followed the the second way you said (pressing "e")  :-) but I can see it now in "view" part as well!

Thanks

Hi Mostafa,

Mostafa A said:

Oh, now I can see the "verilogA" in "view" part!!! I don't know what happened, I just followed the the second way you said (pressing "e") 

Excellent! A refresh or library update may have occurred as a result of your query of the symbol view in your schematic. In any case, I am happy too!

Shawn

Yes maybe.

Thanks a lot Shawn

Mostafa