Thermometer code

Dear sidm,

I use an RTL description which I synthesized to create a schematic representation. The symbol is instantiated in the circuit in which I need a thermometer encoder.

Shawn

It also wouldn't be terribly difficult to write a Verilog-A module if you wanted this to be used in Spectre. Not clear precisely what you needed.

Anyway, I was going to throw one together and then I decided that since you hadn't specified precisely what you wanted it for, I wasn't going to spend time writing it only to find that I'd done something other than your requirement. However, a google search found this example code.

Andrew

Dead sidm,

Andrew, of course, is absolutely correct that a veriloga representation will provide an alternative solution!

A second motivation for using a synthesized RTL representation is that in many applications the relative delay of the thermometer outputs must be considered, Specifically, any slew between the binary weighted inputs may result in skew between outputs and can lead to undesired behavior of the circuit the outputs are driving. By using a schematic representation, one can get a rough estimate of any output skew that may exist  and its impact on the following circuit under test.

I hope this provides a little more insight into the motivation for my use of the RTL/synthesized based approach.

Shawn

thanks for the reply Andrew.

Can you please have a look at the below initial code and suggest if this can be automated using ADE/Explorer/Assembler etc.. ? like for binary code the parametric analysis can generate the sequence itself by defining the control bits as variables and setting their limit as 0 & VDD.

In this thermometer code I start by changing the middle lsb bits first and then move towards changing the outer lsb bits. Similarly for the ptherm bits. The inputv variable changes from 0 to 127 though in the below code I have shown only till inputv=14 as I need to manually extend the code for the other inputv values.

// VerilogA for sts_rfic_top_tb, ndiv_test_ramp, veriloga

`include "constants.vams"
`include "disciplines.vams"

module  phaseshifter_decoder_ahdl(vin,th1,th2,th3,th4,th5,th6,lsb1,lsb2,lsb3,lsb4,lsb5,lsb6);
electrical vin,th1,th2,th3,th4,th5,th6,lsb1,lsb2,lsb3,lsb4,lsb5,lsb6;
input vin;
output th1,th2,th3,th4,th5,th6,lsb1,lsb2,lsb3,lsb4,lsb5,lsb6;

real inputv=0;
real ptherm1,ptherm2,ptherm3,ptherm4,ptherm5,ptherm6,plsb1,plsb2,plsb3,plsb4,plsb5,plsb6;

analog begin
// @(initial_step) begin
       inputv=V(vin);
       if (inputv==0) begin
           ptherm1=0; ptherm2=0; ptherm3=0; ptherm4=0; ptherm5=0; ptherm6=0;
           plsb1=0;plsb2=0; plsb3=0; plsb4=0; plsb5=0; plsb6=0;
            end
        else if(inputv==1) begin
           ptherm1=0; ptherm2=0; ptherm3=0; ptherm4=0; ptherm5=0; ptherm6=0;
           plsb1=0;plsb2=0; plsb3=1; plsb4=0; plsb5=0; plsb6=0;
        end
        else if(inputv==2) begin
           ptherm1=0; ptherm2=0; ptherm3=0; ptherm4=0; ptherm5=0; ptherm6=0;
           plsb1=0;plsb2=0; plsb3=1; plsb4=1; plsb5=0; plsb6=0;
        end
        else if(inputv==3) begin
           ptherm1=0; ptherm2=0; ptherm3=0; ptherm4=0; ptherm5=0; ptherm6=0;
           plsb1=0;plsb2=1; plsb3=1; plsb4=1; plsb5=0; plsb6=0;
        end
        else if(inputv==4) begin
           ptherm1=0; ptherm2=0; ptherm3=0; ptherm4=0; ptherm5=0; ptherm6=0;
           plsb1=0;plsb2=1; plsb3=1; plsb4=1; plsb5=1; plsb6=0;
        end
        else if(inputv==5) begin
           ptherm1=0; ptherm2=0; ptherm3=0; ptherm4=0; ptherm5=0; ptherm6=0;
           plsb1=1;plsb2=1; plsb3=1; plsb4=1; plsb5=1; plsb6=0;
        end
        else if(inputv==6) begin
           ptherm1=0; ptherm2=0; ptherm3=0; ptherm4=0; ptherm5=0; ptherm6=0;
           plsb1=1;plsb2=1; plsb3=1; plsb4=1; plsb5=1; plsb6=1;
        end
        else if(inputv==7) begin
           ptherm1=0; ptherm2=0; ptherm3=1; ptherm4=0; ptherm5=0; ptherm6=0;
           plsb1=1;plsb2=1; plsb3=0; plsb4=1; plsb5=1; plsb6=1;
        end
        else if(inputv==8) begin
           ptherm1=0; ptherm2=0; ptherm3=1; ptherm4=1; ptherm5=0; ptherm6=0;
           plsb1=1;plsb2=1; plsb3=0; plsb4=0; plsb5=1; plsb6=1;
        end
        else if(inputv==9) begin
           ptherm1=0; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=0; ptherm6=0;
           plsb1=1;plsb2=0; plsb3=0; plsb4=0; plsb5=1; plsb6=1;
        end
        else if(inputv==10) begin
           ptherm1=0; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=0;
           plsb1=1;plsb2=0; plsb3=0; plsb4=0; plsb5=0; plsb6=1;
        end
        else if(inputv==11) begin
           ptherm1=0; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=0;
           plsb1=1;plsb2=0; plsb3=0; plsb4=0; plsb5=0; plsb6=1;
        end
        else if(inputv==12) begin
           ptherm1=1; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=0;
           plsb1=0;plsb2=0; plsb3=0; plsb4=0; plsb5=0; plsb6=1;
        end
        else if(inputv==13) begin
           ptherm1=1; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=1;
           plsb1=0;plsb2=0; plsb3=0; plsb4=0; plsb5=0; plsb6=0;
        end
        else if(inputv==14) begin
           ptherm1=1; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=1;
           plsb1=0;plsb2=0; plsb3=1; plsb4=0; plsb5=0; plsb6=0;
        end
        else if(inputv==15) begin
           ptherm1=1; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=1;
           plsb1=0;plsb2=0; plsb3=1; plsb4=1; plsb5=0; plsb6=0;
        end
        else if(inputv==16) begin
           ptherm1=1; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=1;
           plsb1=0;plsb2=1; plsb3=1; plsb4=1; plsb5=0; plsb6=0;
        end
        else if(inputv==17) begin
           ptherm1=1; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=1;
           plsb1=0;plsb2=1; plsb3=1; plsb4=1; plsb5=1; plsb6=0;
        end
        else if(inputv==18) begin
           ptherm1=1; ptherm2=1; ptherm3=1; ptherm4=1; ptherm5=1; ptherm6=1;
           plsb1=1;plsb2=1; plsb3=1; plsb4=1; plsb5=1; plsb6=1;
        end
        else if(inputv==19) begin
           ptherm1=1; ptherm2=1; ptherm3=2; ptherm4=1; ptherm5=1; ptherm6=1;
           plsb1=1;plsb2=1; plsb3=0; plsb4=1; plsb5=1; plsb6=0;
        end
        else if(inputv==20) begin
           ptherm1=1; ptherm2=1; ptherm3=2; ptherm4=2; ptherm5=1; ptherm6=1;
           plsb1=1;plsb2=1; plsb3=0; plsb4=0; plsb5=1; plsb6=0;
        end            
        else  begin
           ptherm1=9; ptherm2=9; ptherm3=9; ptherm2=9; ptherm5=9; ptherm6=9;
           plsb1=1;plsb2=1; plsb3=1; plsb4=1; plsb5=1; plsb6=1;
            end

//end

       V(th1) <+ transition(ptherm1);
       V(th2) <+ transition(ptherm2);
       V(th3) <+ transition(ptherm3);
       V(th4) <+ transition(ptherm4);
       V(th5) <+ transition(ptherm5);
       V(th6) <+ transition(ptherm6);     
       V(lsb1) <+ transition(plsb1);
       V(lsb2) <+ transition(plsb2);
       V(lsb3) <+ transition(plsb3);
       V(lsb4) <+ transition(plsb4);
       V(lsb5) <+ transition(plsb5);
       V(lsb6) <+ transition(plsb6);

end

endmodule

I don't quite understand what you mean by "can be automated using ADE/Explorer/Assembler etc..?". If you're asking if the 12 value can be generated by sweeping a single number, then yes, that could probably be done by writing a SKILL function to do the generation of each bit, but since I don't fully understand the encoding (it seems a rather unusual thermometer to me!) I can't really suggest how you'd do that.

The Verilog-A has a number of problems though:

1. You're reading an input voltage and then using == to compare against integer discrete values. The voltage V(vin) will be a floating point value solved by the simulator, and so the chances of it being exactly the integer value you're comparing against are small - it's bad practice to compare floating point value with == at the best of times, but with simulation it's an even worse idea. It's best to compare with a tolerance to ensure they are in a range.
2. Having the voltage go from 0 to 127V is a bad idea too - that means you're introducing large voltages into a circuit that probably isn't high voltage, and so that can compromise accuracy (for example, errpreset=moderate means that relref=sigglobal, which means that the local truncation error is normalised to the highest voltage in the circuit, which is potentially artificial in this case). This is the kind of modelling that forces you to unnecessarily move to errpreset=conservative when a better modelling approach would make sense. Either make the input a different quantity (not voltage) which has a higher range and higher abstol (maybe), or scale it down to be in the range (say) 0 to 1V.
3. I'm sure there must be a better way of doing the encoding than expanding a huge if/then/else. After all, Verilog-A has the << (left shift) and & (bitwise and) operators, so you ought to be able to left shift an integer a number of times to do a traditional thermometer code - I'm sure you could adapt that to meet your more unusual encoding (maybe it isn't unusual, but I don't recognise it).

Andrew

I don't quite understand what you mean by "can be automated using ADE/Explorer/Assembler etc..?". If you're asking if the 12 value can be generated by sweeping a single number, then yes, that could probably be done by writing a SKILL function to do the generation of each bit, but since I don't fully understand the encoding (it seems a rather unusual thermometer to me!) I can't really suggest how you'd do that.

The Verilog-A has a number of problems though:

1. You're reading an input voltage and then using == to compare against integer discrete values. The voltage V(vin) will be a floating point value solved by the simulator, and so the chances of it being exactly the integer value you're comparing against are small - it's bad practice to compare floating point value with == at the best of times, but with simulation it's an even worse idea. It's best to compare with a tolerance to ensure they are in a range.
2. Having the voltage go from 0 to 127V is a bad idea too - that means you're introducing large voltages into a circuit that probably isn't high voltage, and so that can compromise accuracy (for example, errpreset=moderate means that relref=sigglobal, which means that the local truncation error is normalised to the highest voltage in the circuit, which is potentially artificial in this case). This is the kind of modelling that forces you to unnecessarily move to errpreset=conservative when a better modelling approach would make sense. Either make the input a different quantity (not voltage) which has a higher range and higher abstol (maybe), or scale it down to be in the range (say) 0 to 1V.
3. I'm sure there must be a better way of doing the encoding than expanding a huge if/then/else. After all, Verilog-A has the << (left shift) and & (bitwise and) operators, so you ought to be able to left shift an integer a number of times to do a traditional thermometer code - I'm sure you could adapt that to meet your more unusual encoding (maybe it isn't unusual, but I don't recognise it).

Andrew

thanks a lot Andrew for the details.

The code may not be looking usual because at we are trying a couple of iterations to symmetrically trigger the blocks.