"ERROR: attempt to access a quantity that depends on the time derivative" in Verilog-A

Ramy,

The challenge is that the simulator needs to keep track of the history when computing a derivative, and it's hard to do that when it's embedded within an expression (in this case it's within the argument to tanh). You can workaround this by using a temporary internal node - something like:

V(tempNode[k]) <+ alpha* h*ddt(V(x_node[k]));
I(x_node[k])<+ V(x_node[k]) + (1-alpha)* h*ddt(V(x_node[k])) - tanh(mul_Vin_w_Vin + mul_c_w_Vin + w_rec[j]*(V(x_node[k]) - V(tempNode[k])) + b_node[k]);

You'd declare tempNode as and internal node:

electrical[0:5] tempNode;

Note that you may need to scale the value appropriately to ensure that the voltage is reasonable (I don't know enough about the system or the coefficients to understand the magnitude of the result of this part of the expression). In essence you want the voltages to be similar range to those in the rest of the circuit to prevent convergence/accuracy issues (so probably up to a few volts, no more).

Regards,

Andrew.

Hi Andrew,

Thanks a lot for your explanation.

In the meantime after posting my question, I tried the same idea:

////////////////////////////////////////////
electrical [0:5] d;
//..
for(k=0; k<5; k=k+1) begin
     for(j=0; j<25; j=j+1) begin
          V(d[k])<+ h*ddt(V(x_node[k]));
          I(x_node[k])<+ V(x_node[k]) + (1-alpha)* h*ddt(V(x_node[k])) - tanh(mul_Vin_w_Vin + mul_c_w_Vin + w_rec[j]*(V(x_node[k]) - alpha*V(d[k]) + b_node[k]);
          V(Vout)<+ w_Vout[k] * V(x_node[k]) + b_Vout;
     end
end
/////////////////////////////////////////

> I have a syntax error in the above-bolded part which I couldn't debug. Can you please guide me?

> I understand your point about scaling and that's the purpose of having alpha.

Regards,

Ramy

Hi Ramy,

You're missing a close parenthesis (I've added it back - and highlighted it in red below):

I(x_node[k])<+ V(x_node[k]) + (1-alpha)* h*ddt(V(x_node[k])) - tanh(mul_Vin_w_Vin + mul_c_w_Vin + w_rec[j]*(V(x_node[k]) - alpha*V(d[k])) + b_node[k]);

Andrew

Thanks for debugging this.

After correction, it seems to have the initial error.



Ramy

Thanks for debugging this.

After correction, it seems to have the initial error.



Ramy

Which version of Spectre are you using? In the terminal window type "spectre -W" to find this out.

Andrew

It's 19.1.0.496.isr12

Ramy

I see you made another small change from that image, but even with that, I can't reproduce it (even with the same version of Spectre). Perhaps I couldn't spot a small difference somewhere.

It's probably easier if you post the entire code - at the moment I'm making stuff up around the bit you've shown here, and maybe the problem is dependent upon the context it's in? Hard to be sure (since I can't reproduce it).

Andrew

Dear Andrew,

Basically, the idea is to implement a RNN (Recurrent Neural Network) model in Verilog-A language.
Since Verilog-A is compatible with the simulator, the system of equations derived from the model (like (1) & (2) in the listing below) can be solved.

Let's assume a single-input-single-output model for simplicity. Kindly check below for a sample to what I'm trying to implement:

/////////////////////////////////////////////////////////////////////////////////

`include "constants.vams"
`include "disciplines.vams"

module test ( out, in );

//port declaration

input in;
output out;
electrical in, out;
parameter integer n=5; //n: size of internal nodes
electrical [0:n-1] x_node; //x_node: internal node (hidden nodes)
electrical [0:n-1] d; //d: temperory internal node

//parameters declaration
//below w -> refers to weight, b -> refers to bias, which are the hyper-parameters coming from the learning process

parameter real h=2e-12;
parameter real alpha=0.1;
parameter real w_in [0:n-1]='{0,0,0,0,0};
//parameter real w_rec [0:n-1][0:n-1]= '{'{0,0,0,0,0},'{0,0,0,0,0},'{0,0,0,0,0},'{0,0,0,0,0},'{0,0,0,0,0}}; //not allowed in Verilog-A
//flatten w_rec
parameter real w_rec [0:24]= '{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; //generally [0:pow(n,2)-1] 
parameter real w_out [0:n-1]='{0,0,0,0,0};
parameter real b_node [0:n-1]='{0,0,0,0,0}; 
parameter real b_out=0;

//variables declaration

real c;
genvar i, j, k; //iterators -> declared as genvar to use analog operators within the loop
real mul_in_w_in, mul_c_w_in; // mul -> refers to a product

analog begin

          //1.evaluate c
          c= h * ddt(V(in));

         //2.evalute in*w_in & c*w_in
         for(i=0; i<n; i=i+1) begin
              mul_in_w_in = mul_in_w_in + w_in[i] * V(in);
              mul_c_w_in = mul_c_w_in + w_in[i] * c * (1-alpha);
         end

         //3.evaluate V(x_node)
         for(k=0; k<5; k=k+1) begin
              for(j=0; j<25; j=j+1) begin
                   V(d[k])<+ h * ddt(V(x_node[k]));
                   I(x_node[k])<+ V(x_node[k]) + (1-alpha) * V(d[k]) - tanh(mul_in_w_in + mul_c_w_in + w_rec[j] * (V(x_node[k]) - alpha * V(d[k])) + b_node[k]); //(1)
                   V(out)<+ w_out[k] * V(x_node[k]) + b_out; //(2)
              end
         end
   end

endmodule

//////////////////////////////////////////////////////////////////////////////////////////////

Regards,

Ramy

Hi Ramy,

The issue is because of the assignment to the variable c earlier in the analog block - that's then used in the calculation of mul_c_w_in in step 2, and then that's used within the tanh() in step 3. So it's the same as before - you need to have somewhere to compute the derivative in the matrix. So using the same trick (and I'll leave it to you to play with scaling) solves this - defining cc as electrical (I could have changed c to be electrical rather than real, but I made the node called cc instead), and then:

          //1.evaluate c
//          c= h * ddt(V(in));
          V(cc) <+ h * ddt(V(in));

         //2.evalute in*w_in & c*w_in
         for(i=0; i<n; i=i+1) begin
              mul_in_w_in = mul_in_w_in + w_in[i] * V(in);
              mul_c_w_in = mul_c_w_in + w_in[i] * V(cc) * (1-alpha);
         end

         //3.evaluate V(x_node)
         for(k=0; k<5; k=k+1) begin
              for(j=0; j<25; j=j+1) begin
                   V(d[k])<+ h * ddt(V(x_node[k]));
                   I(x_node[k])<+ V(x_node[k]) + (1-alpha) * V(d[k]) - tanh(mul_in_w_in + mul_c_w_in + w_rec[j] * (V(x_node[k]) - alpha * V(d[k])) + b_node[k]); //(1)
                   V(out)<+ w_out[k] * V(x_node[k]) + b_out; //(2)
              end
         end
   end

Regards,

Andrew

Dear Andrew,

Thanks for your help.

The code went through but I have a problem with convergence where V(out) is fixed at some high value of voltage while it should be transitioning between 0 and 1 V.

-> According to my knowledge, I have to keep the simulation timestep as small as possible to let the system converge.
 
Here, I assume:  t = t_prev + alpha * h 

where h: is a fixed timestep taken during sample generation for learning my model.
           alpha: is a parameter between 0 and 1 to control the simulation timestep (alpha * h).

and it's clear if I set alpha to values close to 1 the system stability deteriorates.

-> Recalling your hint:

"Note that you may need to scale the value appropriately to ensure that the voltage is reasonable (I don't know enough about the system or the coefficients to understand the magnitude of the result of this part of the expression). In essence, you want the voltages to be similar range to those in the rest of the circuit to prevent convergence/accuracy issues (so probably up to a few volts, no more)."

I'm a bit confused about what happened when the time derivative is assigned to the voltage of an internal node and the consequences of this on convergence.
Could you please clarify this point? I would appreciate if you can give an example on how voltage should be scaled.

Thanks in advance for your time,

Ramy

Hi Ramy,

In general you should not need to try to control the timestep within a Verilog-A model - the simulator will do that automatically to ensure the specified simulator accuracy tolerances are met. However, it's possible that you're trying to model some kind of discrete sampled-data system (I've not even tried to spend time looking at the details of what you're actually modelling), but if so you might need to set up some kind of timer/clocking scheme to ensure that this sampled-data behaviour is operating.

The point I had made about scaling the values appropriately is that by using a contribution operator (<+) to contribute the derivative to an internal node (which is marked as electrical), you're then creating an equation that needs to be solved as if it were a voltage (if using V(); it would be a current if you used I()). Given that a Verilog A discipline has two quantities (electrical has the Voltage and Current quantities), and each quantity has controls on the absolute value used in the tolerance criteria used in many places in the numerical algorithms - all of the form:

delta < reltol*value+abstol

The abstol is set differently for each quantity, and is usually set to a millionth of a typical signal value (so vabstol is 1uV, and iabstol is 1pA by default). What this means is that you want the values on these internal nodes to be at similar "voltage" levels to other signals in the circuit - i.e. of the order of 1V.

So I was suggesting you scale the value as part of the contribution statement, given that you can then unscale it when it's used in a subsequent equation. This will keep the algorithms happier, and less likely to introduce errors.

However, that may not be the root cause of your convergence difficulties - you might be advised to contact customer support so that somebody can look at your real example with coefficients and circuit and analysis setup rather than just the model (or simplified versions of the model). Even if you were to post that all here, I don't realistically have the time to check it and respond (I answer here in my spare time as it's not part of my role at Cadence).

Anyway, hope that helps!

Regards,

Andrew

Hi Andrew,

Thanks a lot for the detailed explanation.

So scaling a value could be as an example: V(c)<+ scaling_factor * ddt(V(in)); //c is an internal node

So that any update (delta) should meet the criterion you mentioned above and V(c) converge in the end to a value in the allowed range.

Then wherever V(c) is used, it should be in the form: (1/scaling_factor) * V(c)

Did I get your point correctly?

Regards,

Ramy

Yes, you got my point correctly. 

Andrew